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noise level of Vref

Other Parts Discussed in Thread: ADS850, OPA188

Hi all,

in our design we are using ADS850 ADC . the issue what i am facing is the output is not consistent .

info about design:3482.Design.pdf

1. My operating frequency is 2Mhz.

2. The Vref  what we are providing is from External Opamp(opa188) .

3.   operating is full scale

how much noise level can be acceptable for Vref(in our design it is 70mVp-p). 

attached files are my design.

the modification what we have done is  we have removed Vref decoupling Capacitor(C23). because it was creating noise upto 250mV(100MHz to 1GHz) . expecting some suggestion from your side to get rid of this

thankyou

  • Sharath,


    I've moved this post to the High Speed Data Converter Forum where the ADS850 is supported. I think you'll find an answer here.


    Joseph Wu
  • Hi,

    I do not see a specification on how much noise may be tolerated on the VREF pin.  As this is an old device that came to TI by way of the Burr Brown acquisition many years ago, all I have to go on is what I see in the existing datasheet that is on the web.

    But since the use of an external VREF is usually needed when an application requires better accuracy or drift characteristics than available from the internal ADC bandgap, and since the VREF voltage directly sets the full scale definition for the device, I would expect that any noise on VREF would have the potential to affect the output samples so I would recommend keeping VREF as clean as possible.

    I notice that your schematics do not include the recommended bypass capacitors on REFT and REFB as shown in Figure 5 of the data sheet. As REFT and REFB are generated from the applied VREF, if there is noise on VREF then I would expect that good bypassing of the REFT and REFB would have the potential to filter out some of that noise from the REFT and REFB and maybe settle down the output samples somewhat, helping to take care of what noise was not removed from the VREF signal directly.

    Regards,

    Richard P.