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DAC3482 PLLAVDD causes DACVDD, CLKVDD & DIGVDD (1.2V) to increase to 1.8V

Chetan Maheshwari
Prodigy 190 points
Other Parts Discussed in Thread: DAC3482

Hi,

In one of our application, we are using 2 DAC3482 (DAC A & DAC B). Both the DACs have similar circuitry. The voltages are generated as below:

1 TPS79601DCQ is used to generate 3.3V for IOVDD & AVDD with 3.6V to LDO as input. IOVDD & AVDD are isolated by ferrite beads.

1 TPS79601DCQ is used to generate 1.2V for DACVDD & CLKVDD with 3.6V to LDO as input. DACVDD & CLKVDD are isolated by ferrite beads.

1 TPS79601KTTT is used to generate 1.2V for DIGVDD with 3.6V to LDO as input.  PLLAVDD voltage is sourced from AVDD generated, with a ferrite bead isolation from AVDD.

For DAC A, all the voltages are proper and DAC output is observed.

For DAC B, if PLLAVDD is connected, then the LDO outputs DACVDD & CLKVDD increase from 1.21V to 1.8V and DIGVDD increases from 1.21V to 1.5V.  If PLLAVDD is isolated then all the 1.2 voltages(DACVDD, CLKVDD, DIGVDD) are proper. 3.3V AVDD is properly generated in either case when PLLAVDD is connected or not. Please suggest what could be the reason for this? 

What could be the reason that the 1.2V LDO feedback correction is not happening when PLLAVDD (3.3V) is connected?

  • 0
    TI__Guru* 78744 points
    Chetan,

    One thing to check is the soldering of the DAC3482. If you are using MRQFN package, then it is possible device B has some sort of short on the inner row. MRQFN manufacturing guideline is listed here:
    www.ti.com/.../szza059.pdf

    You mentioned both DAC devices have similar circuitry, but please advise what is different? It is hard to comment without seeing schematics of some sort.

    Also, I would encourage you to post the question on the LDO forum. Certain LDOs require start-up with 0V output. If there are certain bias at the output, the LDO will not start-up correctly.

    The DAC itself does *not* have any start-up sequence.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 190 points

    Hi Kang,

    I have attached schematics for both the DACs.

    Regards,

    Chetan

    DAC3482.docx

  • 0 in reply to Chetan Maheshwari
    Prodigy 190 points

    Hi Kang,

    The available voltage on DAC2 pin PLLAVDD (when not connected to 3.3V) is 0.5V. The impedance between PLLAVDD pin and 1V2 net for DACVDD/CLKVDD is 25.6K. The impedance between PLLAVDD pin and 1V2 net for DIGVDD is 27K. The impedance values indicate no direct short between PLLAVDD and 1V2 net. 

    Could you please suggest something on how this biasing might be happening when connecting this pin to 3.3V and what should be the approach to resolve this?

    Regards,

    Chetan

  • 0 in reply to Chetan Maheshwari
    TI__Guru* 78744 points
    Hi Chetan,

    If PLLAVDD is floating while DACVDD and CLKVDD is enabled, I believe there could be leakage voltage from the ESD cells that brings the PLLAVDD net to 0.5V.

    Some LDOs cannot start if the output node has pre-biased voltage. You will need to check with the power supply team on their forum for detail. For instance, I see the following:
    The TPS796xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
    voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
    to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
    might be appropriate

    Chances are the DACVDD and CLKVDD net reaches at 1.2V before the PLLAVDD LDO even have input voltage. Just a suspicion from my side. Again, as I mentioned before, there is no start-up requirement on the DAC side, as you can see that your DAC1 is operating correctly.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 190 points

    Hi Kang,

    Thanks for sharing your insights.

    I am checking the same in linear regulators forum too.

    I am using same 3.6V net for generating voltages for both the DACs and I have provided big shape in layout for the same. DAC B LDOs are closer to 3.6V generation regulator.

    Sharing one more observation.

    Though datasheet suggests supplying all voltages, I tried some experiment as I am not using internal PLL (working in PLL bypass mode).

    With PLLAVDD for DAC B not connected, I checked for internal test patterns and it passed. When I try for Tx output, I get alarm_dacclk_gone in config5 register. External DACCLK 1GHz is probed and is fine. 

    Could you please suggest if this voltage is a must even in PLL bypass mode? Also how is FIFO Out Clock (internal to DAC) generated? Could you please share more information on figure 56 in datasheet?

    Regards,

    Chetan

  • 0 in reply to Chetan Maheshwari
    TI__Guru* 78744 points
    PLLAVDD is needed for internal DAC core clocking path. FIFO out clock is generated internally and need PLLAVDD.

    Test pattern test the input path only thus can get away without PLLAVDD running.

    -Kang
  • 0 in reply to Kang Hsia
    Prodigy 155 points

    Hi,

    Any suggestion for above issue?

  • 0 in reply to murugan ramasamy
    TI__Guru* 91947 points

    Murugan,

    We were unable to duplicate this on our EVM. Can you provide more details on how you did this? Did you notice this after power up? Did this occur after configuring the DAC? Was this on a TI DAC3482EVM or your custom board? If it was your custom board, can you send the schematics?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 155 points

    Hi,

    Its a custom board,Please find the DAC section schematic in the attachment.

    We are using 2 DACs in a same board,

    DAC1 is always working fine.which is working at 125Mhz

    DAC2 most of the time working fine(which is working at 500Mhz) ,few times while powering on the DAC2 configuration itself not happening.

    For more detail Please check the previous post in this same issue.

    Please provide your feedback.DAC3482_SCH.docx

  • 0 in reply to murugan ramasamy
    TI__Guru* 91947 points

    Murugan,

    Your schematic looks fine. Please make sure your board is not populated with "DAC34H82" parts as these have a different pinout.

    I would suggest you remove FB22 on DAC #2 and provide the PLLAVDD with an external supply. I would be interested in seeing how much current is drawn when you have the situation where this supply causes the others to go up to 1.8V. There also is a chance you may have damaged this part which could possibly cause this issue. Have you tried replacing this DAC?

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 155 points
    I will try by using external power supply.
    I dont think DAC damaged ,because most of the times its working fine.very few times this problem observed
    DAC replacement experiment already i done but still i have issue.
    If you have more suggestion please share .

    Thanks your suggestion,
  • 0 in reply to murugan ramasamy
    TI__Guru* 91947 points

    Murugan,

    Make sure to issue a DAC reset after power up every time.

    Regards,

    Jim