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ADC12J4000: wrong data received at receiver

KGY
Intellectual 300 points
Other Parts Discussed in Thread: ADC12J4000, ADC12J4000EVM, LMK04828

hi,

i am connecting the ADC12J4000 to virtex 7 and are currently facing some problems receiving correct data at the receiver.

when i set the adc to short transport  test mode, i will receive correct data in Lane 01,2,4,5 and 6. however lane3 and lane 7's data is always not correct. when is switch to ramp test mode, error also occur in lane3 and lane7.

Below is the configuration of the ADC and receiver core: 

ADC

Fs = 4GHz

K=4

F=8

L=8

D = 1 (DDC bypassed)

DDR : 1 (DDR Rate)

P54 : 0 (5/4 PLL Disabled)

Sysref = 25MHz

receiver

Xilinx JESD204 v6.1 (virtex 7)

GT Ref clock =  200MHz

Sysref = 25MHz 

Any idea what is wrong?

  • 0
    TI__Mastermind 44680 points

    Hi KlJ

    I believe that the Xilinx FPGA/firmware needs 2 different clock frequencies for that linerate. Please refer to section 6 of the TSW14J10EVM user guide:www.ti.com/lit/pdf/slau580

    At 4 GHz clock, the lane rate is 8 Gbit/sec. Therefore the clocks to the FPGA should be as follows:

    GT REFCLK = 8000 / 20 = 400 MHz

    Core Clock = 8000 / 40 = 200 MHz

    SYSREF = 8000 / (10 * F * K) = 8000 / 320 = 25 MHz

    If you are using the ADC12J4000EVM you will need to modify the divider for the GT REFCLK from 40 to 20. If you are using your own ADC12J4000 hardware you will need to adjust your GT REFCLK frequency generation as needed.

    If making this change doesn't resolve the errors you are seeing, please let us know.

    Regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Guru* 91947 points

    ADC12J4000, TSW14J10, VC707,Fs_ 4G.pptxKIJ,

    Attached is a document showing how we configured the ADC12J4000 when running in bypass mode, Fs = 4G, and using the TSW14J10EVM with the VC707 Xilinx platform.

    Regards,

    Jim

  • 0 in reply to jim s
    Intellectual 300 points
    Hi Jim
    Thanks for your reply. I follow your suggestion however it does not resolved the errors.
    I was using GT REFCLK = 200 MHz and Core Clock = 200 MHz from different output of LMK04828 previously.
    Even if I change the GT REFCLK = 400 MHz, I am seeing the same wrong data on Lane 3 and lane7.
  • 0 in reply to KGY
    TI__Guru* 91947 points

    KL,

    Do you have all of the lanes polarity reversed in your FPGA firmware? All of the lanes have the P and N swapped on the EVM and we un-swap them with the HSDC Pro GUI software.

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 300 points
    Hi Jim,

    I did not invert the lanes.
    I have connected the LMK04828 SDCLKout13 (25MHz) to FPGA sysref, SDCLKout9 (25MHz) to ADC sysref, SDCLKout11 (200MHz) to FPGA core clk, DCLKout10 (200MHz) to GT refCLK. below is my configuration sequence for ADC and LMK04828:

    ADC12J4000
    0x0021 0x00 // Initiate reset of all registers
    0x0021 0x01 // De-assert reset
    0x0030 0xC0 // SYSREF receiver and processor ON
    0x0040 0x04 // Set serializer pre-emphasis for high speed PCB
    0x0066 0x03 // Foreground calibration mode with timing optimization enabled
    0x002B 0x13 // Change reserved register to proper setting
    0x0208 0x03 //
    0x0051 0x84 // Calibration optimized for large signals
    0x0201 0x0E // Scrambler off, KM1 = 3, DDR, JESD disabled
    0x0200 0x30 // bypass mode, 2's complement
    0x0202 0x44 // P54 PLL off, Differential SYNC, ramp test
    0x0058 0x04 // test pattern on
    0x0201 0x0F // Scrambler off, KM1 = 3, DDR, JESD enabled
    0x0050 0x0E // Initiate a foreground calibration

    LMK04828
    0x000 0x80
    0x002 0x00
    0x120 0x04
    0x121 0x55
    0X123 0X00
    0x124 0x22 //set SDCLKout9 to SYSref output
    0x125 0x00
    0x126 0xF0 // enable SDCLKout
    0x127 0x11

    0x128 0x0A // DCLKout10 = 200MHz
    0x129 0x55
    0X12B 0X00
    0x12C 0x02 // set SDCLKout11 to device clock output
    0x12D 0x00
    0x12E 0xF0 // enable SDCLKout
    0x12F 0x11

    0x130 0x0A
    0x131 0x55
    0X133 0X02
    0x134 0x22 // set SDCLKout13 to sysref output
    0x135 0x00
    0x136 0xF0 // enable SDCLKout
    0x137 0x10 // disable DCLKout12

    0x138 0x40
    0x139 0x03 // continuous SYSREF
    0x13A 0X0
    0X13B 0X50 // set SYSREF to 25MHz
    0x13C 0x00
    0x13D 0x08
    0x13E 0x03
    0x13F 0x00
    0x140 0x01 // disable SYSREF pulser
    0x141 0x00
    0x142 0x08
    0x143 0x32
    0x144 0xFF
    0x145 0x7F
    0x146 0x18
    0x147 0x00
    0x148 0x02
    0x149 0x02

    Is there anything wrong in the configuration which could cause the errors?
    i am using continuous SYSREF. Can i ignore the SYNC pin of LMK04828?
  • 0 in reply to KGY
    TI__Mastermind 44680 points

    Hi Kl

    Are you using the ADC12J4000EVM, or is the ADC on a board of your own design?

    Is the capture board a Xilinx development board, or a board of your design?

    Regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Intellectual 300 points

    Hi Jim,

    all on my design board.

  • 0 in reply to KGY
    TI__Mastermind 44680 points

    Hi Kl

    The errors on specific lanes could be due to inadequate serial data eye opening at the FPGA GT receivers.

    1) Try decreasing or increasing the ADC12J4000 serializer pre-emphasis setting (Register 0x040h, Bits 3:0) to see if the error behavior changes. The current setting you are using may be too low or too high for the link distance and PCB dielectric material of your board.

    2) Try decreasing the clock rates. Instead of 4000 MHz, try a lower ADC DEVCLK frequency. (reducing all related clocks by the same ratio) If reducing the serial interface bit-rate eliminates the errors they are most likely due to issues with signal quality on those 2 lanes at that speed.

    I hope this is helpful.

    Best regards,

    Jim B