dac1220

NEHA PARMAR65

Other Parts Discussed in Thread: DAC1220

Im using DAC1220 for my project. I have generated the DAC_CLK and DAC_SCLK from the FPGA clock which is 10MHZ.

After this a delay of 100us is generated, in this Delay the DAC_SLCK and DAC_CLK is set to '0'.

After the delay is completed i have made a signal pin that is set to '1'. This pin I am using for starting the process of sending the data to SDIO after the delay.
Falling edge of the SDIO a count is started so that at each count the bits of INSR1(for CMR),CMR1,CMR2,INSR2(for DIR),DIR is send.

1. I am sending the INSR1 for the CMR (MB = 01(2 bytes) and A3 A2 A1 A0(0101)), thus DAC will interpret that CMR is selected the the next 8 bits will the instruction for CMR1,then i am sending the CMR1(10111100) which has BD is '1' which means that the address will be decremented.

2. Then DAC will decrement the address and the wait for instruction for the CMR2 thus i send the CMR2(11100000) . after this I am sending the instruction to jump in the DIR address through INSR2(01000010) which has MB= 10(3 bytes) and A3 A2 A1 A0 = 0010 and then i send the data for conversion to the DIR of 24 bits through the SDIO. after this i am ending the the process and if statement which i was using to check the each count value and on that count i was sending bits to SDIO i.e. I am running this only one time not repeatdly

I am sending the INSR1,CMR1,CMR2,INSR2,DIR of 24 bits to the sdio at each count (the count which is incremented at falling edge of DAC_SCLK).

Now my doubts are whether the A3 A2 A1 A0 is to be set in the INSR1,INSR2 as it is not mentioned anywhere? If i am stopping the process after one conversion i am still getting the repeated pattern on the SDIO pin.
And if i changed the DATA of DIR(24 bits for conversion) i am still getting the same voltage at VOUT = vref, showing no change if the digital bits of DIR are changed.

For repeated proecess whether i have to send the INSR1,CMR1,CMR2,INSR2 repeatedly and only once?

The main problem is in simulation i am obtaining the results on SDIO one time means only for one conversion bits are shown but in real approach i am getting the repeated patterns which it was supposed to be send only one time. I tried it to send on some random pin of FPGA in that also repeated pattern is generated.

Can you go through my program and help me in this. If my interpretations are wrong somewhere please guide me in that.

i am attaching the vhdl code for it and the schematic of device.

THANK YOU.

Fullscreen ti_problem.txt Download

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:44:27 05/10/2016 
-- Design Name: 
-- Module Name:    dac_sts - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
                use IEEE.STD_LOGIC_ARITH.ALL;
                use IEEE.STD_LOGIC_UNSIGNED.ALL;
                use IEEE.numeric_std.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dac_sts is
    Port ( CLK_CRY : in  STD_LOGIC;
           DAC_SCLK,DAC_CLK : out  STD_LOGIC;
			 DAC_CS : OUT STD_LOGIC := '0';
			 GPIO_OUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ;
           DAC_SDIO : inout std_logic
           );
end dac_sts;

architecture Behavioral of dac_sts is

signal dac_count:  std_logic_vector(24 downto 0) := "0000000000000000000000000";
signal dac_cnt,dac_cot : integer range  0 to 95 := 0;
signal dac_delay : integer range 0 to 10000 := 0;
signal pn,pn1,pin : std_logic := '0';
signal dac_sclk_cntr : std_logic := '0';
SIGNAL adc_reg : STD_LOGIC_VECTOR(23 DOWNTO 0) := "000000000000000000000000"; 


begin

process(CLK_CRY) 
begin
		if rising_edge(CLK_CRY) then
			dac_count<= dac_count+ 1;
			dac_delay <= dac_delay + 1;
		end if;
				 DAC_CLK <= dac_count(1);
				 DAC_SCLK <= dac_count(4);
				 dac_sclk_cntr <= dac_count(4);
				 
		if dac_delay <= 1000 then
			DAC_SCLK <= '0';
			DAC_CLK <= '0';
		elsif dac_delay > 1000 then
		pn <= '1';
		end if;
		
end process;


process(CLK_CRY,dac_sclk_cntr)
begin
		if pn = '1' then
 
					if falling_edge(dac_sclk_cntr) then
									dac_cnt <= dac_cnt + 1;
					end if;
						 
		end if;
						if dac_cnt = 1 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 2 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 3 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 4 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 5 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 6 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 7 then
						DAC_SDIO <= '0';
												

						elsif dac_cnt = 8 then
						DAC_SDIO <= '1';
					-----------------------------------------------------------

						elsif dac_cnt = 9 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 10 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 11 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 12 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 13 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 14 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 15 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 16 then
						DAC_SDIO <= '0';
						------------------------------------

						elsif dac_cnt = 17 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 18 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 19 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 20 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 21 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 22 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 23 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 24 then
						DAC_SDIO <= '0';


----------************insr for dir************---------------
						elsif dac_cnt = 25 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 26 then						
						DAC_SDIO <= '1';

						elsif dac_cnt = 27 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 28 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 29 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 30 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 31 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 32 then
						DAC_SDIO <= '0';

----------------------------------------------

						elsif dac_cnt = 33 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 34 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 35 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 36 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 37 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 38 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 39 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 40 then
						DAC_SDIO <= '1';

						
						elsif dac_cnt = 41 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 42 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 43 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 44 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 45 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 46 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 47 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 48 then
						DAC_SDIO <=  '0';
						
						elsif dac_cnt = 49 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 50 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 51 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 52 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 53 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 54 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 55 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 56 then
						DAC_SDIO <=  '1';

						else
						DAC_SDIO <= '0'; 
--						pn <= '0';
						end if;				

end process;




end Behavioral;

.orcad_offset2.pdf

over 9 years ago

0 Joseph Wu over 9 years ago

TI__Guru* 98025 points

Neha,

What is the CLK and SCLK frequency that you are using for the DAC1220? You mention that it is generated by the 10MHz clock coming from the FPGA. I don't really know VHDL, but it looks as if you're adding a count each time, so you have a divide by 2 and are using a clock frequency of 5MHz. If that is the case, you're still running the clock too fast. From the Digital Interface Section, the max fXIN frequency is 2.5MHz. While the characteristics of the device are defined mostly at this max frequency, I don't think it will operate much faster than that. Also for the SCLK frequency, the device will won't operate much faster than 500kHz. The timing table says that the SCLK frequency should be 1/5 of the master clock frequency.

I see that you're using the ADuM7640 as an input isolator, is there a reason that you didn't use the +5VDA for pin 20? Based on my reading of the datasheet, it should be able to level shift the output voltages. I was concerned that the output of the ADuM7640 wouldn't get the VIH high enough for the DAC1220. This is likely ok, because the VIH min level is 2.0V, but you should verify that the input signal makes it this high.

Also, I think you have the ADuM7640 connected wrong. Note that the input from the uC shows DAC_CS connected to VIB, which goes to the SDIO pin on the other side. I think you've swapped the DAC_CS and DAC_SDATA lines for this device.

Again, I don't read VHDL well, but it looks as if you have data transitions at the falling edge of the SCLK. I would note that the device is reading the data at the falling edge of SCLK, so you want the data to be there and setup on the rising edge of SCLK. This is something you want to check with an oscilloscope or logic analyzer.

Going on to your numbered points:

1. It does look like you're writing to the register and you are sending '00100101'. However, the address for CMR1 is 4 not 5. It looks like by sending '0101' you're writing to CMR0 which is the LSB of the command register and then to a reserved register. Note that there is no CMR2 (I assume you are referring to CMR0) and by missing the count, you haven't written to the correct register to set the BD bit.

2. Again the second command looks correct, but you write to address '0010'. Since the first command is suspect, you may not be decrementing the counter with a bad write to the BD bit in the CMR.

To debug this. I would start by only reading the register back start by reading the CMR1 and CMR0 registers and check to see that the default back. Once you are able to do this, try writing to the CMR registers and then them back to verify that the communication was correct.

In your previous post, I asked for oscilloscope plots to check your timing. I still think this is a necessary step. I also asked some questions about the signals you are measuring, and I think that would also be important to know. When you post back, I'd like to see a reply to those questions.

Joseph Wu

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