ADS5401 / Input clock range

Hi,

Please take a look at Figure 26 in the data sheet for performance over clock amplitude.  We tend not to put a minimum value on clock amplitude because larger clock amplitude is better (because of sharper clock edge, primarily) and the performance begins to suffer with smaller clock amplitudes, and Figure 26 lets you choose for yourself where you would like to set your minimum clock amplitude depending on how much performance you would be willing to give up.    Max clock amplitude is generally not an issue, unless you exceed the absolute maximum specifications. 

Regards,
Richard P.

Hi,

Yes, that figure would be for a sinewave input clock.  And yes, slope is the important parameter.   But we can only characterize our devices with a sinewave clock, because there is not a signal generator available with low enough phase noise for us to characterize a data converter to the kind of SNR that the data converter is capable of unless we use a narrow-band bandpass filter to remove as much of the phase noise from the signal generator as possible.  and if we use a bandpass filter to filter out phase noise, we also filter out harmonics even though we are not trying to filter out harmonics.    and if we used an active element such as a buffer device to 'square up' the signal again, then the active element would have its own jitter performance that would again become a limiting factor in our device characterization of SNR.

But still, we have not characterized the device with an LVDS signal, so I cannot say that the sharper edge rate would completely make up for the lower amplitude.  I do not have any characterization data to support such a tradeoff.

Regards,

Richard P.