Other Parts Discussed in Thread: ADC12J4000, LMK04828, ADS42JB69
A few days ago, TI released High Speed Data Converter Pro GUI Installer, v4.50 (Rev. Q) which supposedly includes support for reading ADC data from a ADC12J4000EVM using the Xilinx KCU105 Eval board.
There is also a rough draft of a manual( e2e.ti.com/.../3073.KCU105-User_2700_s-Guide-rough-DRAFT.pdf ) it in another thread: e2e.ti.com/.../523947
I have not yet managed to get this working. Here is my procedure:
0) Connect the ADC12J4000EVM directly to the FMC HPC as seen in all pictures
1) Close the jumper on the ADC12J4000EVM labeled KC705 JTAG (otherwise you cannot use the KCU105 JTAG because it gets forwarded over FMC)
2) Flash the bitstream C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\KCU105 Details\Firmware\KCU105_TI_DHCP.bit to the KCU105 using Vivado's Hardware Manager
3) Launch ADC12J4000EVM GUI and click "Program Clocks and ADC" (do I have to make extra settings on the Low Level View here?)
4) Check the DHCP IP using the KCU105 UART (or looking at the firewall)
5) Launch HSDC Pro GUI 4.50, connect to the IP
6) Select ADC12J4000_BYPASS in the ADC dropdown
7) In the field ADC Output Rate type 4G and click somewhere else. A message pops up: "New lane rate is 8G due to ADC Output Data Range change. JESD reference clock from Device EVM to KCU105 needs to be set at 200M"
8) In the Analysis Window dropdown, I select 32768
9) Click capture. Error Window pops up: "Read DDR to file <linebreak> TIMED_OUT_ERROR <linebreak> Time out error"
The leds show the following state:
0 on, 1 off, 2 on, 3 blinking slowly, 4-6 blinking fast, 7 on
My questions are:
A) Has the software been tested with the combination of KCU105 and ADC12J4000EVM?
B) If so, what am I doing wrong?
C) Are there any additional tricks I can do to get more debug information?
D) Is the KCU105 firmware that is bundled with HSDC 4.50 identical (design and SDK code) to the JESD204B Hardware Demo from Xilinx's JESD Lounge (JESD204B_UltraScale_Hardware_Demo_2016_1_v1.3.zip)? If not, where can I get it?
E) From what I read, LED 0 being on signifies JESD RX Sync. This is on. LED1 should signify JESD TX Sync, that is off. Is it normal in this configuration that only RX syncs, not TX? (presumable because the ADC12J4000 does not really receive data using JESD?)
F) After completing the steps outlined above, should ADC be already flowing towards the FPGA? Or does that have to be initialized by the PC software? (I am thinking about going around the TI GUI and using the Xilinx Python functions to get data from the DDR memory)
G) From my understanding, ADC12J4000EVM by default uses a clock of 2GHz which gets divided by the factors that you can set in the "Low Level View"-Tab, LMK04828 registers 0x100 and 0x110. Currently I am leaving both at their default values, 0xA for 0x100 and 0xA for 0x110.
For my previous experiments using VC707, I had to use 0x5 in the 0x110 register. Am I correct in not changing these?
Thanks in advance, Max
Some additional debug information:
Platform info:
Windows 10 x64 10.0.14393
Vivado 2016.1
UART Output:
------------------------------------------------
-----UltraScale Hardware Demo for JESD204B------
------------------------------------------------
SW Version 2.1.006
HW VERSION = 1.5.3
For board KCU105 built with TI EVM support
Initialising platform
..DRAM capture buffer..
Max Buffer Size = 0x20000000 bytes..
..IIC and SI570..
Set SI570 frequency to =156250000 Hz
..Jesd204 PHY..
TX freq=6250, xMult=4, PLLtype=0, band=0
RX freq=6250, xMult=4, PLLtype=0, band=0
..Data IF..
..INTERRUPTS..
..SW register interface..
..Ethernet Interface..
Start PHY autonegotiation
Waiting for PHY to complete autonegotiation
Autonegotiation complete
Waiting for Link to be up; Polling for SGMII core Reg
auto-negotiated link speed: 1000
Board IP: 192.168.100.179
Netmask : 255.255.255.0
Gateway : 192.168.100.100
UHWD Jesd IP server started @ port 80
..Eyescan SW..
Platform Ready
------------------------------------------------
freeing arg...
closing tcpb...
Set speed for TX, PLL=0, xMultReal=40, xMultIdx=4, freq=8000MHz pllBand=0
Set speed for RX, PLL=0, xMultReal=40, xMultIdx=4, freq=8000MHz pllBand=0
Writing LPMEN = 0
