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ADC12J4000: ADC12J4000

Itai Eden1
Intellectual 330 points
Part Number: ADC12J4000
Other Parts Discussed in Thread: LMX2592EVM,

Hi,

I'm using the LMX2592 to drive an ADC (ADC12J4000)and a DAC at 2.7GHz. 

The two are driven from the same output of the LMX (the 2nd output is occupied) so my solution is to use 2 resistive splitters (one for RFOUT_p and one for the RFout_n).

The ADC clock is then composed of one of each splitter output. same goes for the DAC.

I'm using PD0030SM resistive splitter (DC-30GHz BW)

I simulated the clock in Hyperlinx (post layout):

The simulation was conducted in Hyperlinx using the LMX & ADC ibis models & Splitter S-parameters model (.S3P).

The relevant nets were exported to Free form schematic.

- The green wave is the signal when transferred through the Splitter (PD-0030SM).

- The blue wave is the signal when transferred without the splitters (simply removed from the free form schematic)

(see attached file for figure)

It is noticeable that the slew rate is somewhat effected by the splitter.

Questions:

1. Do you think such degradation would affect the ADC performance?

2. Is it possible to roughly predict by how much?

Best regards,

Itai

  • 0
    TI__Guru* 91947 points

    Itai,

    I would suggest using an ADC12J4000EVM in external clock mode, and drive it with an output from a LMX2592EVM that is going through this splitter. This may not be your best option but I think it would tell you exactly what you want to see. Another option is to use a signal generator that is feeding a balun or transformer, then send this to the splitter. 

    Regards,

    Jim S.

  • 0 in reply to jim s
    Intellectual 330 points
    Hi,

    The ADC12J4000EVM does not have an option for external differential clock input. So, I'm afraid the results will not tell me much about the "real" differential clock comparison (with and without splitters).

    Can you comment on the simulation clock signals (with and without a splitter) that I attached to the original post?
    Do you think that the slew rate degradation will have a significant effect on the ADC performance?

    Thanks,
    Itai
  • 0 in reply to Itai Eden1
    TI__Mastermind 44570 points

    Hi Itai

    The answer may depend on the frequency of your input signal.

    If the reduced slew rate results in higher jitter at the ADC clock inputs it could impact the SNR of the converted waveform at higher input frequencies.

    Best regards,

    Jim B