DAC39J84: There is no data out

Christine,

What family is the Xilinx device? Is this a custom board? Are you passing CGS (Sync asserted high by DAC)? What is you DAC sample rate? What is your reference rate used by the DAC PLL? Have you tried getting an output from the DAC using just the NCO to make sure the analog portion of the DAC is working properly? Attached are some documents that may help you. 

Regards,

Jim

5327.DAC3xJ8x Device Initialization and SYSREF Configuration.pdf2287.DAC39J84_NCO_NO_SYSREF.pptx

Jim,

Thanks for your message.
The family of the Xilinx device we used is 7 series. And ,yes,this is a custom board.
I have passed CGS, Sync asserted high by DAC.
The DAC sample rate is 1GSPS.And the reference rate uesed by the DAC PLL is a 500MHz clock.
I haven't tried the test you suggest, I'll try it today.
I tried the "PRBS TEST" , every lane tested ,the ALARM pin is high.

Christine,

Tell me the following and I will try to duplicate your setup with our hardware:

1. Virtex or Kintex device

2. LMFS settings

3. Data input rate

4. Interpolation factor

5. SYSREF frequency

6. DAC PLL settings (VCO select, N div, M div, prescalar, JESDCLK div, SERDES div)

You may want to run without the DAC PLL to start with to get the link established. Attached are a couple more documents to help you.

Regards,

Jim

DAC PLL Guide.pptxDAC38J84 Clock and SERDES Configuration.docx 

Jim,

1. Virtex or Kintex device
The FPGA is Virtex 7.
2. LMFS settings
LMFS=8411.
3. Data input rate
The data input rate is 1000MSPS.
4. Interpolation factor
The interpolation factor is 1.
5. SYSREF frequency
The SYSREF frequency is 250MHz/64 (3.90625MHz).
6. DAC PLL settings (VCO select, N div, M div, prescalar, JESDCLK div, SERDES div)
VCO select =4GHz, N div = 2, M div = 2, Prescalar = 4 , JESDCLK div = 2, SERDES div = 2


Yours,
Christine.

Christine,

If your reference clock is 500MHz, your value for N is wrong. It needs to be set to 1. Use a value of 20 for K. Also make sure the following are correct:

VCO Tune = 20  (Config108 0xE)

CP Current = 12.5mA  (Config51 0xA878)

Serdes MPY = 5 (Config60 0x28)

Clock Alarm should read 0x2 at Conf108

Regards,

Jim

Jim,


Thanks for your help.We can get signal from the DAC output port now, but the amplitude is too small , I don't know why.

The reference clock I said is DACCLK/N, a 500MHz clock. We use LMK04828B to output a 1GHz clock to DACCLK ,and set N = 2.

I read config108 ,the value is 0x2, so I think the PLL is locked.

About the value of K, I can't understand why it should be 20 , I set it 32 . Is it wrong?


Yours,
Christine

Christine,

For K, you could use either 20 or 32. Just make sure the value matches on both ends. Do you have DAC gain set to max (Config3 0xF080)? Do you have a 1.92K resistor between RBIAS (pin G10) and GND?

Regards,

Jim  

Jim,

Thank you very much.

The resistor between RBIAS and GND didn't weld correctly. We weld it again,and the amplitude become normal.


Yours,
Christine