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ADC12J4000: Multi-ADC SYNC (or Multi-ADC-board SYNC)

new2day
Expert 1940 points
Part Number: ADC12J4000
Other Parts Discussed in Thread: LMK04828, TRF3765, ADC12DJ3200, LMK00301, , LMX2582

In ADC12J4000 EVM, there is TRF3765IRHB for higher ADC clock above ~3GHz. 

I like to confirm what my understanding is right, 

1. To meet the DEVCLK (ADC clock) and the SYSREF relationship for multi-ADC synchronization with TRF3765, one of the output from TRF3765 will have to be sent back to the FBCLK input of LMK04828. 

2. In the other word, by doing so to have multi-ADC or multi-ADC12J4000 EVM to be synchronized when using TRF3765 as ADC clock. 

Thanks.

  • 0
    TI__Mastermind 44680 points

    Hi new2day

    There are usually a number of possible configurations for synchronizing multiple ADCs.

    Unfortunately synchronizing multiple ADC12J4000 with Fclk at 4000 MHz is tricky since the divided down SYSREF and FPGA clocks from each LMK04828 cannot be easily synchronized.

    Before I try to answer your specific questions, do you need to synchronize multiple ADC12J4000EVMs or are you trying to design a multi-ADC12J4000 system with the converters synchronized?

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1940 points

    I'm trying to design a system that having multi-ADC12J400 (or ADC12DJ3200 for example) on multi-board with all ADC synchronized between the boards and systems. 

  • 0 in reply to new2day
    Expert 1940 points

    Any updates? Thank you.

  • 0 in reply to new2day
    TI__Mastermind 44680 points

    Here is an example clocking four ADC12J4000 devices on a single board, feeding data to one FPGA.

    This method includes a way to fine-tune the clock applied to each ADC to optimize alignment of the sampling instants of all converters.

    2 or 4 ADC clocking.pdf

    If you want to synchronize multiple boards, each with multiple ADCs then you can use a central clock source distributing a signal at F_SYSREF. This will be the reference clock input to the LMK04828 in the previous example. The LMK04828 devices will operate in zero delay feedback mode to enable aligning them to the common reference.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1940 points

    1. Why was LMK00301 needed. 

    2. Was Figure 5 applicable or feasible from TI's app: slyt638? - what shown in Figure 5 is most like what's on the ADC12J400EVM. 

    3. There are too many PLLs + buffers required if do what's shown in the "2-or-4-ADC-clocking.pdf". It won't fit on our board. 

    One of my original question is about the reason of bring one of the TRF3756 to FBCLKin of the LMK04828 on ADC12J4000EVM.

    Was it for having TRF3756 output phase aligned to LMK04828 or wise versa? Since TRF3756 has no SYNC function or feature.

    It's true if use LMX2582. Thank you very much.

    slyt628_sync_jesd204.pdf 

    Regards.

  • 0 in reply to new2day
    TI__Mastermind 44680 points

    Hi

    One output of the TRF3765 is sent to the LMK04828 CLKin1 inputs and used as the clock source for the DCLK/SDCLK circuit block. This signals is at ADC DEVCLK/2. Dividers are set to generate the required FPGA clocks and the SYSREF for the FPGA and ADC. By default the ADC SYSREF is disabled, but it can be enabled by adjusting the settings for the SDCLKout11 output. This architecture allows the ADC DEVCLK frequency to be easily adjusted and not dependent on the VCO frequency limitations of the LMK04828. The LMX2582 could be used in this same architecture in place of the TRF3765.

    In a real system based on this architecture the ADC RDEL setting would be used to adjust the relative timing of DEVCLK and SYSREF until setup and hold is met properly. There will be some skew variation between these signals due to the propagation delay through the LMK04828 divider and distribution circuit. If the skew variation causes setup/hold to become unacceptable then the RDEL value would need to be adjusted as a function of system temperature.

    The example circuit I shared earlier has the benefit that it can adjust the relative skew between the ADC DEVCLK signals. This would need to be done if the exact sample timing of the multiple ADCs must be exactly aligned. The ADC does not have an aperture delay adjustment internally and this is the only way to adjust the relative timing between multiple 4 GHz clocks. If exact sample timing alignment is not needed then a single 4 GHz clock generator can be used and a fan-out device used to distribute the multiple 4GHz clocks to the ADCs.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1940 points
    Hi Jim,

    Appreciated your feedback. I'm kind of considering to have another clock generator and distribution board.
    Other than SMA/MMCX, individual or ganged, do you have any recommended small profile type connectors (DP preferred) for clocks at this rate?
    I know Samtec have a lots of high-speed connectors and like to get your opinion about it. Thank you very much.
  • 0 in reply to new2day
    TI__Mastermind 44680 points

    Hi

    As long as the connectors and associated cables are rated for the frequencies of interest they should work OK. I'm not familiar with the DP characteristic you are referring to.

    Huber+Suhner has a number of ganged coaxial connectors (MXPxx series) for high density applications.

    Best regards,

    Jim B