Part Number: DAC38J84
Other Parts Discussed in Thread: LMK04828,
We have an application were we want to interpolate data clocked by the internal PLL on the DAC38J84. We are using a 3.party circuit board with similar configuration as the evaluation board (with an LMK04828).
I have looked at the register settings generated from the DAC3XJ8X GUI program for different interpolation settings using the Quick Start tab and see that the program changes the clock output decimation factor on register 0x108 of LMK04828 with the decimation and do not use the internal PLL of the DAC38J84.
In addition the program changes registers 0x00, 0x25 and 0x3B on the DAC38J84 (interpolation and division of serdes and JESD clocks).
I would however expect that the increased rate could be accomplished by clocking up the internal PLL instead of increasing the frequency of the input clock?
We successfully generate waveforms (for example) at 320 MHz in baseband and have also managed to generate interpolated signal by clocking the DAC from the LMK at 2 or 4 the sample speed.
We also generate waveforms successfully with the PLL enabled and output clock is the same as the output clock.
However when we enable the PLL with a ratio of 2 or 4 with the same interpolation set, we get no output.
When doing this, we read back that the lane skew (Reg 7) is changed from 3 (at interpolation=1) to 0.
The PLL tuning is verified by reading back register 0x31, and we have changed the registers 0x25 and 0x3B accordingly to the interpolation. (PLL clock ratio 2 @320 MHz: M=4, N=2, P=8, VCO_tune=44, H-Band VCO)
Have we misunderstood something?
Regards
Stig
