ADS1232: FIR Filer for stable reading from ADC

Hi Sandeep,

welcome to our forum and thank you very much for your interest in ADS1232.

Ideally the raw codes should not fluctuate by more than about 27 counts with your settings:

Noise_PP(@Gain=64, DR=10SPS) = 125nVpp
LSB Size = (2 * VREF/2) / (64 * 2^24) = 4.66nV
125nVpp / 4.66nV = 26.8 Codes

I believe we need to look into you schematic and probably also layout first to understand why you are not achieving datasheet performance so far. Would you mind posting your schematic of the ADS1232 here?

Did you record and plot the raw codes over time to see if you might have any 50/60Hz noise pick up?

What is the max. capacity of your load cell? And what do you mean by '6 reading order'?

Regards,

Hi Joachim,

Thanks for the reply.

I have not done the recording of raw count with time hence I will do the same.

I am enclosing my schematic along with the post. I will try to upload layout also.

Feed through caps used in circuit are 0.1 uf and polarized capacitor is 100uf at ref pins and 10uf,Tantalum at DVDD

Capacity of load cell is 10kg.

I intent to take 6 reading for computation while using  FIR filter. It takes around 600 ms for this and I can update the display in 1 second.

Regards

S Agashe

Adc card.pdf

Hi Sandeep,

thanks a lot for the additional information and for sharing your schematic.
Some of your capacitor values seem to be pretty large. But they are most likely not the root cause of the higher than expected noise you are seeing.

Following just some general guidelines:

• The differential filter capacitor (C24) should be 10x to 20x larger than the common-mode capacitors (C25, C26).
• It is good practice to place small 100nF power supply decoupling capacitors right next to the supply pins in parallel to the large bulk capacitors.
• I would probably place the large capacitor C18 at the load cell connector and then use similar RC filter values on the reference inputs as on the analog inputs.
  That way the time constants of the RC filters between the analog and reference inputs are better matched. That usually improves things in a ratiometric measurement system.

Regards,

Hi,

I will make the necessary changes in ckt.

Is 4 layer board must for this application?

I covered adc part by metal enclosure but it has not done much.

Will FIR filter really help me?

Should I use ferrite bead inductors in the ckt. for filtering. Especially while  connecting analog and digital ground together.

At present it is made common at 1232 ic pins

Regards

S Agashe

Hi Sandeep,

we have customers who achieved satisfactory noise performance with ADS1232 using a 2-layer PCB. But it is more challenging and in many cases a metal shielding was necessary. A 4-layer board would usually be preferred to have a solid GND plane.

Digital post filtering can improve your results but it would be better to find out why you don't achieve results which are closer to datasheet performance in the first place. Could you send me a data log of a few hundred continuous conversion codes?

Placing ferrite beads between the analog and digital GND connection is actually a very bad idea. This could lead to potential GND differences and eventually destroy the ADC.

Your problem is most likely layout related. In many cases we actually recommend a single GND plane for analog and digital GND and not a split GND. We will gladly have a look at your layout if you manage to post it here.

Regards,

Hi Joachim,
I will send the plot of readings in continuous conversion mode.
Regards
S Agashe

Hi Sandeep,

alright. As a starting point it would be best if you could provide the data with the inputs shorted to mid-supply.

Regards,