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ADC32RF45EVM: FPGA core setting and EVM programming

Kashyap Vanparia
Prodigy 100 points

Part Number: ADC32RF45EVM
Other Parts Discussed in Thread: ADC32RF45, LMX2582

I am trying to interface ADC32RF45 evm with ZC706 board. I have set following parameters for ADC in GUI LMFS=4421, Deimation = 20, internal clocking LMX2582 clock to ADC, sampling frequency = 2457.6MHz, K-1=15. On FPGA side my parameters are F= 2,K=16, Line rate = 2.4576Gbps and Ref clock = 122.8MHz. But my core is not getting data. Also on board I have observed that only PLL2LOcked LED is glowing while LMKlocked LED is not glowing. Please guide me on this issue

  • 0
    TI__Guru* 91947 points

    Kashyap,

    Attached are two examples of the ADC32RF45EVM interfacing to the ZC706 using the TSW14J10EVM interposer board from TI. I am not sure if you are using this third board or not, but it allows the user to run our HSDC Pro GUI on several different Xilinx FPGA development boards, including the ZC706. If you are not using this interposer board, there is some example source code and documentation under the Xilinx website. Information regarding this can be found in the documents attached. 

    Regards,

    Jim

    Xilinx example firmware.docx4274.JESD204_TI_reference_design.pdfZC706 ADC32RF45 82820 Setup.pptx

     

  • 0 in reply to jim s
    TI__Mastermind 29220 points

    Hi,

    If you are using the ADC32RF45 EVM with the SPI GUI that comes with it, and the configuration files that come with the SPI GUI, then you probably have the SYNC signal inverted.   There is a line in the config file for the ADC that you would need to edit out:

    0x0058 0x20     // SYNC polarity inverted as the hsdcpro.ini inverts the sync

    The ini file for our HSDCPro has a line in it that inverts the polarity of SYNC, and since at the time of the release of the EVM there were many copies of that ini file out there, we inverted the polarity of the SYNC in the config file for the EVM in order to match what HSDCPro expected to see.   Your FPGA development platform code is probably not expecting to see SYNC inverted, and so the EVM should not output inverted SYNC either.     You probably are seeing a constant stream of K28.5 codes as the FPGA is holding the ADC in a SYNC state while the EVM is waiting for the SYNC to toggle.  

    Regards,

    Richard P.

  • 0 in reply to jim s
    Prodigy 100 points

    Hi Jim,

    Thanks for the guidance, I got the reference designs. But I don't have the interposer board.

  • 0 in reply to Kashyap Vanparia
    TI__Guru* 91947 points

    Kashyap,

    If you want to test these boards together and use the HSDC Pro GUI, you will need to purchase a TSW14J10EVM. If you want to use the example code provided by Xilinx, you should be able to plug directly into the FMC and use Vivado and Chipscope to review the results.

    Regards,

    Jim