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ADC12D500RF: ADC12D500RF - Spurious at 2Fin

kirty
Prodigy 60 points
Part Number: ADC12D500RF

Hi All,

I am using ADC12D500RF ADC in my design. IF frequency is 200~300MHz & sampling frequency is 500MHz. Sampling frequency(500MHz), is coming from clock synthesizer AD9517-3ABCPZ. Output power of clock synthesizer at 500MHz is given to ADC which is -16dBm, the second harmonics was coming at 998MHz with with -36dBm & third harmonics was coming at 1.5GHz with -21.21.7dBm.I am operating in Non-demux, DESI mode. ADC is giving data in DDR format and DCLK is 250 Mhz in both I and Q channels.

ADC is operated in non-ECM.ADC data(4096 samples) is captured using ISERDESe2 in KINTEX-7 FPGA for characterisation purpose. I & Q-Data is time-interleaved and written to BRAM. The captured data is plotted in wavevision and observed that along with input frequency(Fin), spurious frequencies are observed at 2nFin. 
The same is observed when ADC is operated in ECM. The data output from ADC is set two's complement and captured the data and again plotted and observed same issue.

Attached zip file contains ADC and Clock Synthesizer Schematic, ADC sampled data wavevision plots. 

Please help me to resolve the spurious frequency coming at 2Nfin(N=1,2,..)ADC-Harmonics.pdfnonecm_non_demux_des.zipecm_non_demux_des.zip

  • 0
    TI__Mastermind 44680 points

    Hi kirty

    Thank you for the detailed description of your system and the problem you are experiencing.

    The most common reason to have high harmonics in the converted data is the input signal itself. Most RF signal generators will have relatively high levels of energy at harmonics of the main output frequency. For this reason we always use band-pass or low-pass filters in the input signal path to remove these harmonics, ensuring good measured ADC performance. Please check the input signal using a spectrum analyzer, and add a filter to remove unwanted harmonics.

    The next most common reason with this family of ADCs would be failure to run the device calibration procedure once the device is configured and at a stable operating condition. Please confirm you are running the on-command calibration process after the device is at a stable operating temperature (within 10-20 degrees C of the final temperature) in the configured mode, with clock applied, etc.

    The next reason for high levels of harmonics, particularly even-order harmonics would be imbalance in the analog signal path leading up to the ADC. At the schematic level I notice you have a 100 ohm resistor (R147) at the output of balun T2. Since this is a 1:2 balun, the output impedance will be 100 ohms differential, which is the proper impedance to directly drive the 100 ohm differential input of the ADC. If R147 is installed it will result in a total load at the balun output of 50 ohms differential, which is not matched to the 100 ohm output. Please ensure R147 is not installed. Imbalance in the circuit layout can also cause problems. If possible please provide the layout for the analog signal path leading up to the ADC inputs.

    One other issue I see in your schematic is that all 4 VBIAS pins of the ADC are connected together in a common net, which is then connected to the 4 100nF decoupling capacitors. The proper configuration is to have each decoupling capacitor individually connected to the associated VBIASI or VBIASQ pin with a separate net. Having the VBIASI pins connected to the VBIASQ pins can cause problems with functionality and performance.

    Please let me know the results of your investigations.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44680 points

    Hi Kirty

    I did think of one other common problem that I have encountered.

    If the data from the I and Q output buses is re-interleaved in the wrong order, a similar FFT will be seen.

    You are operating in non-Demux DES mode. When the data buses update one sample from DQ and one from DI are output. The DQ sample is the one that is captured earlier in time, and the DI sample is captured later in time. Please ensure when re-interleaving and processing the data that you are using that sample order.

    Best regards,

    Jim B