ADS7251: Output Delay Time

Umberto Frangi

Part Number: ADS7251

Hi,

my customer is detecting a delay at the outputs(pins 11,12) that is outside the datasheet specs of 15 nsec for TD_CKO.

The value , as you see in the file , is about 27 nsec.

The outputs are connected thru a series resistor of 55Ohms to I/O pins of ARTIX 7 Xilinx FPGA and the capacitive load is quite small.

Do you have any idea about the possible cause of this issue?

Power supply voltages are within the limits.

Thanks

UmbertoADS7251.docx

over 8 years ago

0 Evan Sawyer over 8 years ago

TI__Expert 3175 points

Hi Umberto,

Has the customer tried removing the 55 ohm resistors and replacing them with 0 ohm/wire?

Is there anything else connected to these digital lines (another device or passives) aside from the resistor and FPGA?

0 Umberto Frangi over 8 years ago in reply to Evan Sawyer

TI__Expert 4045 points

4162.ADS7251.docxHi Evan,

the customer removed the series resistor, leaving the output unconnected, but the results are similar to the previous one; see attachement.

Thanks

Umberto

0 Evan Sawyer over 8 years ago in reply to Umberto Frangi

TI__Expert 3175 points

Hi Umberto,

Can you please try lowering the DVDD supply of the ADC to 3 or 3.3 V? While DVDD is not violating the power supply range, the performance is tested for a DVDD up to 3.6 V. It may be that the timing is also based on a lower supply range.

0 Umberto Frangi over 8 years ago in reply to Evan Sawyer

TI__Expert 4045 points

Hi,

the customer cannot do DVDD changes, because the voltage is supplied by a fixed output regulator.

But he noticed that there is a discrepancy between what is said at datasheet page 8 for Td_ckdo, that is calculated from ck rising edge to data output , and what appears at page 22, where it seems the data are shifted out with ck falling edge.

Which is the right sentence?

If data are referred to falling edge, then the delay is < 15 nsec and everything is fine.

Can you clarify?

Thanks

Umberto

0 Umberto Frangi over 8 years ago in reply to Umberto Frangi

TI__Expert 4045 points

Hi Evan,

can I get your answers about the above points?
thanks

Umberto

0 Evan Sawyer over 8 years ago in reply to Umberto Frangi

TI__Expert 3175 points

Hi Umberto,

I will loop you into an email with the designer for clarification on the timing specs.

0 Evan Sawyer over 8 years ago in reply to Evan Sawyer

TI__Expert 3175 points

Hi Umberto,

Per our separate email thread, the data is launched on the falling edge as shown in table 2 on page 22.

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ADS7251: Output Delay Time