ADS8881: Unstable interface with ADS8881

Alex M62

Part Number: ADS8881
Other Parts Discussed in Thread: ADS7042, ADS7854

Hello!

Here is my Verilog HDL code: http://paste.org.ru/?x2a6yj

I trying to work with ADS8881 ADC and it's interface very often getting stuck. FPGA is Xilinx XC6SLX9 with 140 MHz clock speed (to meet 70 MHz clock maximum for ADS8881). Sample rate is 500 KHz and signal is sine at 525 KHz. Every 20-50 us interface hangs up and I restart cycle again. Byte ganged up interface I mean that ADC is not react on control signals. After cycle restart I see it continue to work as expected and then after 20-50 us the error repeats again =(

Also I see another error (take a look at left half of picture below: din=1, dout=orange, sclk=green, convst=red) - sometimes my module false starting to capture data, however dout erroneously getting back to level 1. Right half of picture shows normal cycle without error.

I tried many modes from datasheet: 3 wire 4 wire all with busy or without, and see that ADC working not stable. This makes my cry, what I doing wrong? Modeling in Xilinx ISIM and Modelsim shows that everything is OK with my code - many different measures with random 18-bit values with random conversion times from 500 to 700 ns - all is fine in HDL simulator, but not with real ADC =(

May be someone could share his code to me and all others? I can provide much more details if necessary. Please help, I spent many weeks to get it working stable. Which debug ideas I can try more?

over 8 years ago

0 Luis Chioye over 8 years ago

TI__Guru 55466 points

Hi Alex,

Unfortunately, we don't have a software example for the Xilinx FPGA. If you could please post a few zoomed in oscilloscope plots of the DIN, SCLK, DOUT, CONVST during the read transaction and let us know which mode of operation you intend to use 3-Wire/4-Wire with/or without BUSY so we can verify the interface timing.

Please place the oscilloscope probes right at the pins of the ADS8881 device; and provide oscilloscope plots when the device is properly providing conversion results and for the case when it is not working.

The ADS8881 (18-B) is a very high resolution, very low distortion device, and will not perform as expected for input frequencies above Nyquist. The datasheet shows performance up to 100kHz input frequency.

Please post an schematic showing the ADS8881 digital interface connections as well as the amplifier driving the device.

Thank you and Best Regards,

Luis

0 Jury Pimenov over 8 years ago in reply to Luis Chioye

Prodigy 20 points

Hello!

I made ads8881 to capture 1007 khz at 1000 ksps rate. It showed pure 7 khz sine. Luis, where did you got information that the device will not perform above Nyquist? I see BW parameter claimed to be 30 MHz in datasheet. Isnt it the BW of input circuit?

But anyway, the issue of unstable interface remains actual. Is there any connection of interface unstability with input signal above Nyquist?

If someone has more detailed working alghoritm of stable data capture, we'd be grateful.

0 Jury Pimenov over 8 years ago in reply to Luis Chioye

Prodigy 20 points

Hello!

Why do you think that working abowe Nyquist is impossible?

0 Alex M62 over 8 years ago in reply to Jury Pimenov

Prodigy 30 points

You're absolutely right - since input bandwidth of this ADC is 30 MHz then input signals above 1 MHz is appropriate. When I used 1050 KHz input sine at 1 MHz sampling rate on this ADC it shows me clear 50 KHz sine. My colleague using different ADCs in this mode without any problem.

0 Alex M62 over 8 years ago in reply to Luis Chioye

Prodigy 30 points

Unfortunately I do not have fast enough oscilloscope (I have it only at work, not at home). But I'm able to capture ADC interface lines at higher speed - my picture above is a result of such capture that has been transferred through UART from FPGA to PC.

At another forum people suggested me to try to use interface mode "3-Wire CS Mode Without a Busy Indicator (DIN = 1)" from picture 51. I tried this mode long time ago without success, now I will try this mode again and will post pictures of interface plots where errors occured. Give me few days to try another mode :)

If I will get my HDL code to work nicely with ADC - I will share it in this topic for others.

0 Luis Chioye over 8 years ago in reply to Alex M62

TI__Guru 55466 points

Alex,

The classic SAR ADC architecture can be used to convert input signal frequencies above Nyquist, (undersampling applications); and I have supported systems using SAR ADC's in undersampling applications many times in the past.

The great majority of mid performance SAR ADCs (12-B, 14-B and in some cases, some of the 16-B resolution devices) could be well suited for these undersampling applications where the bandwitdh of the sample-and- hold is in general a limitation on the input frequency (although, of course, as expected, there is a gradual degradation on the performance, as the input frequency increases, and strictly speaking, it will not meet the datasheet specs).

However, SAR ADC's in this performance class, offering very high resolutions with very low distortion (18-B and above resolution) incorporate self-correction algorithms while performing the Least Significant Bit (LSBs) decisions, and will show a more abrupt decrease in performance at the higher input frequencies, at frequencies well below the BW of the sample-and-hold; as the last few bit decisions will be incorrect after a frequency threshold, at frequencies well below the BW of the sample-and-hold.

Therefore, I recommend mid precision SAR ADCs for under-sampling applications for this reason; and I do not recommend 18-B devices for undersampling applications. Well suited devices for under-sampling applications will be for example ADS7854, ADS7042.

There is of course, no correlation between the input frequency and the interface issues .

Thank you,

Regards,
Luis Chioye
Precision SAR ADC Applications

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ADS8881: Unstable interface with ADS8881