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WEBENCH® Tools/DAC38RF84: RF DAC design Bench

Part Number: DAC38RF84
Other Parts Discussed in Thread: DAC38RF82EVM

Tool/software: WEBENCH® Design Tools

Hi,

I can not find any section in Webench designer regarding RF DAC.

or alternately, is it possible to get  access to a similar GUI than the one with DAC38RF82EVM to help designing an architecture ?

Best Regards

  • Hello, we do not have our high speed converters in the WebBench tool. If you let me know a little more about what questions you have I can try to put together some resources to figure it out.

    The GUI can be run in demo mode, and has some features available in that mode.

    Regards,
    Brian
  • If you have any other questions about your high speed converter design please let us know.
    Regards,
    Brian
  • Hi Brian,

    thank you for your answer,

    I am trying to define the different parameters for the SerDes PLL knowing the DAC clock frequency and the Baseband input rate.
    do you think that the demo mode of the GUI could help me with that?

    The SERDES PLL VCO must be in the nominal range of 1.52625-3.125GHz according to the data sheet .
    But does it mean with the field rate at the maximum (rate11), i can only get a maximum speed lane of 3.125*2GHz (page 41)?
  • F,

    The GUI will take of all of the serdes parameters for you. After loading the quick start tab page of the GUI, you can then save the register settings using the low level tab page. If you are running with the rate setting at 00 (full rate), the serdes pll would be running at 3.125GHz, but the serdes block will be processing 4 samples per clock cycle which will equal to a lane rate of 12.5Gbps (see Table 2).

    Regards,

    Jim

  • Hi,
    thank you for the feedback
    How do you get the GUI please?
    Regards
  • F,

    Go the DAC38RF82EVM product folder on the TI website. You can down load the GUI from here. The EVM and GUI covers all of the parts in this family.

    Regards,

    Jim

  • Hi ,
    I have installed the GUI and did the quick start config.
    I would like to read the Serdes Clock Configuration Register (address=0X3B) .
    I am going in Low Level Vi tab but can only see the registers with a name with config* and there is none at the address 0X3B.
    Where should i go in the GUI to check the content ofthis particular register please?

    Regards
  • F,

    This address is in the general  register page.To address this page, the upper address byte needs to be set to "4".  See the attached slides. You can also open a log file when using the GUI by double clicking in the lower left corner of the GUI. This log file will show all address written to when ever you make changes to the GUI.

    Regards,

    Jim

    Serdes register 0x3B.pptx

  • Hi,

    I am looking at the EVM GUI v2p0 as shown below

    It looks that the SERDES REF= DAC_PLL/( PRESCALAR* DIVIDER)  following the red wire path.

    On the data sheet, i can not see the Prescalar behind the DAC_PLL output. Can you please explain to me the difference?Prescalar has a fixed value of 4.

    Best Regards