• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 46 subscribers
  • Views 669 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC088S022: Serial Timing

Seishin
Genius 4135 points
Part Number: ADC088S022

Hi,

My customer is using ADC088S022 for their products.

One bit of data missing has occurred about once every 20 minutes.

DOUT changes from high to low during SCLK high.

Do you know the reason for timing abnormality of DOUT?

Best regards,
Seishin

  • 0
    TI__Guru**** 175471 points
    Hi Seishin,

    Do you have actual traces that you can share with us? The figures above are very nice, but it would be helpful to see captures from either a logic analyzer or an oscilloscope.
  • 0 in reply to Tom Hendrick
    Genius 4135 points
    Hello Tom,

    Thank you for your reply.

    If it's possible,I want to send the waveform as a private message.

    Best regards,
    Seishin
  • 0 in reply to Seishin
    TI__Guru**** 175471 points
    Hi Seishin,

    Did you ever send that detail along? Feel free to PM me if you feel its necessary.
  • 0 in reply to Tom Hendrick
    Genius 4135 points

    Dear Tom,

    Sorry for not getting back to you sooner.

    Please find the attached document.

    ADC088S022_Waveform.pdf

    Pert Number :ADC088S022
    Test condition：SCLK：1.5MHz　(1cycle=66.6us)

    【Normal】

    SCLK￣￣＼＿＿／￣￣＼＿＿／￣￣
    DOUT＿＿＿／￣￣￣￣￣＼＿＿＿＿

    tDACC :(DOUT Access Time after SCLK Falling Edge）
    ・Data Sheet Specifications 17ns typ.　27ns max.
    ・Observed value 20ns-10ns=10ns

    tDHLD：(DOUT Hold Time after SCLK Falling Edge）
    ・Data Sheet Specifications 4ns typ.
    ・Observed value 40ns-10ns＝30ns

    【Bad】

    SCLK￣￣＼＿＿／￣￣＼＿＿／￣￣
    DOUT＿＿＿／￣￣￣＼＿＿＿＿＿＿

    tDACC：
    ・Observed value 20ns-10ns＝10ns
    tDHLD：
    ・Observed value -320ns-10ns＝-310ns

    Best regards,
    Seishin

  • 0 in reply to Seishin
    TI__Guru**** 175471 points
    Hi Seishin,

    Thank you for the plots! Can you please tell me more about the note regarding the 'DOUT is observed at the FPGA output...'? By the DIN, the next channel to be sampled is CH4, is this always the case during abnormal operation? Also, can you get the analog version of these control lines? The plots you sent look like they are from the LA side of the MSO4034.