ADS1248: ask for the reasonable explication about the aliasing or another thing

Samuel,

First, I'll post your question transcribed from your doc:

Dear sir,

When using the ADS1248IPWR in our application, we can not get the reasonable explication about the aliasing. Our external analog filter and circuits are show as below.

Fig 1. External analog filter and circuits

And

But when we add the noise signal by signal generator from 32K, 64K, 96K, 128K…800K（400mvpp）. we got the temperature fluctuation as flow.(PS: ADS1248 work @20 sps,16 gain, and S type TC @800℃)

Fig 2. temperature fluctuation

According to the signal attenuation, the noise @64KHz and 128KHz has much smaller amplitude than @32KHz, but they have greater temperature fluctuation. @64K, it similar has 0.33mV voltage change.

My question are:

Is there any character inside ADS1248 cause the issue? Is there any reasonable explication for the issue?

Dear Joseph

Thank you very much for your nice answer. However, it seems the phenomenon is not well explained.

As you told us, according to aliasing, if the modulation clock is 32KHZ, the multiple of 32Khz components will aliased to 0 hz. One worry of you is how close we feed the signal to multiple of 32khz. We already test this carefully, adjusting the frequency near the 32khz, 64khz, 96khz, 128khz, 160khz,..., and found the response is similar to what we already show to you.

From the picture we show to you, it seems the modulator frequency is 64khz. Since if we assume modulator frequency to be 64khz, the phenomenon can be explained more reasonably. At multiples of 64Khz(64khz, 128khz, 196khz,..), the disturbance is dominant and drop linearly(here, the response of the PGA is also added, so seems not linearly, but more likely to be proportional to 1/f^2). Could you please help check this? Under 20sps, it the modulator work under 64KHZ?

B/R

Samuel

Dear Joseph

As we already told you in the last message that we already adjust the frequency near the multiples of 32khz, and the phenomenon is the same as we already show to you. So, deviation of frequency shall not be the root cause of the phenomenon.

What we do is as follows: we use external 4.096Mhz oscillator, and with 50ppm tolerance. We use AFG3022C signal generator to feed the disturbance. At each multiple of 32KHZ, e.g., at 32KHZ, we adjust the frequency of the signal generator around 32KHZ, with resolution of 1HZ, and sweep between 32KHZ-50HZ to 32KHZ +50HZ. The maximum output disturbance is what we show you in the picture. And what 's more, we found at 32KHZ -50HZ and 32Khz+50HZ, the output become very flat, which means the digital filter works. And we can even found that the output fluctuation at several frequency points follows the rule of the digital filter curve(drop as frequency deviates from 32KHZ).

So, could you give us some more reasonable explaination?

Some more thinking and guess from our side:

We still assume the modulator works at 64KHZ. However, if everything is ideal, then there shall be no output fluctuation(or shall be much lower than what showed in the picture, since the digital filter have very high suppression at 32KHZ if modulator frequency is 64KHZ). So, we must found some reasonable root cause for this phenomenon.

One thing we do is: we doubt whether the 32khz added disturbance contain 64KHZ harmonics. To verify this, we increase the 32KHZ by 25hz. So, if harmonic is the problem, then if added disturbance is 32K+25, then harmonic shall be 64K+50hz. Since 64K+50 fall in to the notch, it will be significantly suppressed. However, we found the decrease is only 3 to 4 time, which seem harmonic is not the key factor. And we even measure the 32k disturbance and measure it with oscillascope and do FFT analysis, however, we found the harmonic is very low, almost negligible. So, it seems harmonic is not the key reason.

Second thing we do is: we doubt whether intermodulation is the problem maker of the output fluctuation at 32KHZ. Since, disturbance 32KHZ and maybe some internal 32KHZ(derived from external 4.096MHZ) may modulate each other, and generate 0HZ and 64KHZ component. And these component will fully contribute to the output. This seems possible, we do not find any violates till now.

Anyhow, all the above we do is thinking and guess, we need you to give us some more precise explanation to make our design more confident.

One guess is, the modulator works at 32khz, but samples twice(with 180 phase difference with each other)? 

B/R

Samuel

Hi Samuel,

As Joseph has already stated, the modulator operates as shown in Table 9 of the ADS1248 datasheet. At 20sps this is 32kHz. The only other consideration is the random PGA chopping. This may result in an additional intermodulation effect.

If you want more confidence in your design, I'm not sure what more we can add. It would appear that you are heavily relying on the digital filter to remove higher frequency content. Your test approach is adding a large noise source as a differential signal. This would be unusual, as most external noise will be picked up as common-mode noise on thermocouple wiring. Also, the test schematic configuration appears to place the input outside of the common-mode input range for the ADS1248 at a gain of 16.

To increase your confidence in your design, I would suggest altering your input filter to lower the cutoff frequency. You could also use a 2nd order RC filter to steepen the cutoff. I would also consider specific types of noise sources and realistic frequencies as input test cases. This may be EMI/RFI sources and power line-cycle frequencies. 32kHz +/- 50 Hz and multiples thereof are not very realistic values in any application that I can think of, especially at the magnitude of noise your are using.

Best regards,
Bob B

Dear Bob

Yes, adding more filtering(lower the cutoff frequency, using second order filters) can make the noise suppression better. However, every measure has its pros and cons. Adding more filtering means more stable time needed when doing multiplexing among channels, thus make the refresh time longer. This is also a key index which we can not sacrifice too much.

The phenomenon we measured(32KHZ output fluctuation lower than that of 64KHZ) from ADS1248 now is different from what we and even your think in mind, or precisely, is different from what the theoretical results tells. If modulation clock is 32KHZ, then by adding the same amplitude of noise of 32KHZ and 64KHZ, the 64KHZ output fluctuation must not be so higher than that of 32KHZ(64KHZ have more suppresion than 32KHZ by the external RC filter, and for the PGA, 64KHZ GAIN must not higher than that of 32KHZ). However, what the real phenomenon shows is exactly different from the theoretical result tells. Then there must some explanation for this.

Another ponint i want to emphasize is that, you said 32KHZ+-50HZ and multiples are not realistic in field, but i want to tell you that we must take care of such point of frequencies. The reason is, we already faced a lot of real field cases, in which frequency inverters is the main disturbance source. And the frequency inverter works between several tens of kiloHZ to several hundreds of kiloHZ. 32KHZ and its multiples falls exactly in this sensitive frequency range.

Our situation now is that, by adding the fitering already showed in the first message, we can get an accepted noise suppresion result in the field. However, what we worry about is, as you see the 64KHZ fluctuation showed now is much higher than that of 32KHZ, and if this characteristic or feature is not a reliable one(e.g., in some other samples of ADS1248, or in another batch of ADS1248, 32KHZ output fluctuation will be similar, ot higher than that of 64KHZ ), then maybe the suppression in such batch of ADS1248 will be get lower, which will cause problem in the field. That's what we want you to give us a reasonable explanation of the phenomenon, and thus make us feel more confident for our design.

Thank you very much for you strong support, and looking forward to see your reply!

B/R

Sameul

Hi Samuel,

The specific information you are requesting is not something that we would normally characterize as it is a condition to be avoided. In the case of switching power supplies we would suggest avoiding frequencies at or in multiples of the modulator frequencies.

If you have an externally generated source (inverter, etc.) that is radiating 200mVpp (or more) of noise, which is an order of magnitude greater than the voltage you are measuring, you have a problem. If that voltage is not adequately filtered and is then gained up by an amplifier, you could potentially leak that undesired voltage into your measurement.

As this is the first time in the 10+ years of the life of the part that we have had a question about the aliasing as it relates to the modulator rate, we will need to do some more examination to understand the results you are seeing. I will attempt to duplicate your test setup.

Best regards,
Bob B

Dear Bob

For the external noise, what we observed is way large than what you said 200mv, the maximum peak to peak value we observed is even 5V! However, if we do proper filtering, the milivolts TC signal can be measured accurately!

The 10+year experience can not prove that this is not important. Everything is changing in the nowday world. So, there is always new problems we need to tackle. Yes, in the field, you can have some more measures to avoid such problem, e.g., make the invertor cable far from the TC to reduce the coupling; using TC transducer for each TC channel(then more filtering can be added since there is only one channel), and convert them to 4 - 20ma signal to send to the DCS modules; etc. However, to make the product more competive, we need to solve this problem in the 8 channel TC module, to make the field problem solving more efficient, more cost effective, more reliable. That's why we need this information. And we think TI as a famous semiconductor company know how know why in this point, wand we can rely on you to make it clear!

Thank you very mcuh for your strong support! Looking forward to see your reply.

B/R

Sameul

Hi Samuel,

I spent long hours in the lab today looking at the ADS1248 and driving the input with a large voltage at the modulator frequency (and multiples of the mod frequency). I see a much different looking response when using the internal oscillator as opposed to an external 4.096MHz clock. I think there may be some clock coupling from the external source. Due to the drift of the internal oscillator it is difficult to make good comparisons. This will take a lot more time to study, so please be patient.

Best regards,
Bob B

Dear Bob

Tnank you very much. We will wait for your patiently.

Thank you again!

B/R

Sameul

Samuel,

For whatever reason the plots for input signals at 0.14Hz, 32kHz, 64kHz, 96kHz, and 128kHz didn't make it through the posting. I'll show them again here:

0.14Hz:

32kHz:

64kHz:

96kHz:

128kHz:

Joseph Wu

Dear Joseph

Thank you so much for your so detailed explanation! Really appreciate your support for us!

First of all, for your concern about DC coupling, we do exactly the same as what you did in the experiment. So, no problem here. For input signal range, we also make it in the dynamic range of the PGA. Also, no problem here.

We doubt whether the duty cycle of the 32Khz modulator clock is the root cause of phenomenon. If modulator clock duty cycle is exactly 50%, then the 32Khz and its odd multiples, shall be deeply suppressed to a very minimal value. However, here the results show that odd multiples of 32Khz still have some fluctuations. And the duty cycle of the 32KHZ modulator click can explain this well. Do you think so?

B/R

Shihuan

Shihuan,

I did a quick check on the measurements near 32kHz and I found that as I move in 10Hz increments around that point, the measurement that I see is a local maximum at 32kHz. It also basically fits the same shape as a replication of the DC frequency response from 0 to 100Hz. Starting with 32kHz, I get this data:

At 32.010kHz, I get this

At 32.020kHz, I get this:

Putting together a series of data, I get this result if I normalize the 32kHz frequency result and change to a dB scale:

There are two things that this tells me. First, there is a local maximum at 32kHz and that the local miminums are close to the expected values at ±50Hz and ±60Hz from the 32kHz frequency with the replication at the mod clock frequency. It doesn’t show the exact same frequency response, but the noise floor is too high from the input source. Second, if the modulator was running at 64kHz, the 32kHz would certainly be a zero showing. Based on those two results, (and I know the filter length and data rate based on the accumulation), The modulator is certainly running at 32kHz.

Now I’m not exactly sure why the odd harmonics are suppressed. I’ve talked to some of the designers here and there are a couple of possibilities. First, the double sampling of the input during a single modulator clock might have something to do with it. This is also complicated by the fact that the sampling is not just a simple double sample, but there are multiple phases in the sample that allow for faster settling. Also, there may be non-linear effects in the PGA that cause other artifacts in the sampling and therefore the frequency response. It was also suggested that because the PGA input is basically using a function generator to apply an input signal on AINP, while holding AINN constant, that the common-mode rejection is not 0. This might cause other artifacts from the PGA if the common-mode signal is not able to keep up with the PGA. In my best guess, I still think that the windowing from double sampling and a less than 50% sample for each half of the full modulator clock may be the cause.

Regardless, the best solution is to implement an anti-aliasing filter at the front end. If this does come from a non-linear effect from sampling or from some artifact from the PGA, filtering would remove this rather easily.

Joseph Wu