THS1207: Separate Conversion and Data output

Hi Robin,

Welcome to our e2e forum! I'm not specifically aware of anyone using four THS1207 devices in parallel like this, but there is no real reason why it would not work. Also, depending on your controller, you might consider using the THS1206 instead. If you are using an FPGA or other state machine based controller, the THS1207 is fine, just keep in mind that you have to READ data synchronously with the CONV_CLK. The THS1206 has an output pin called DATA_AV, which can be used like an interrupt on a micro controller.

With either part, you can use an address decoder chip like the SN74AHC138 to control the CS0 input on the THS120x devices. Four parts can share a common CONV_CLK (CONVST) and then you would use two address lines from the uC or GPIOs from an FPGA to select which of the four devices you want to read from.

For the second question, this family of devices does not have an internal power-on reset so there are no specific 'default' register state, you have to manually reset the device after power up. Figure 30 in the THS1207 datasheet and Figure 34 in the THS1206 datasheet provide the initialization sequence.

Hello Tom,

thank you for your fast reply. I made a rough schematic of how i want the Conv_Clk signal to be. Please use this information to review your answer. I also looked into the datasheet of the THS1206 and it seems that the only difference from the THS1207 is its circular buffer. I assume that they have similar caracteristics because they are from the same famlily. Can you also answer me what the SYNC output of the THS1207 is usually used for?

I didn't understand how you can achieve a serial read out from multiple ADCs like you mentioned. Can you describe the read out process in more detail please? Schematic.pdf

Hi Robin,

Besides the buffer, the THS1206 has an internal conversion clock option, while the THS1207 does not. The conversion clock on the THS1207 is meant to be a free running clock, so the 'pauses' may have an impact on the conversion results. The SYNC pin on the THS1207 basically let's you know when you are aligned with CH1.

If you are using a DSP or other micro controller with a proper parallel EMIF type interface, there should be address lines associated with that databus. Two address lines would connect to the inputs of the address decoder. Four of the outputs of the address controller would then connect to the CS0's of four ADC's you are trying to talk to giving each of them their own address. You would just read 4x from each 'address' to retrieve your data. The reading of data in this case does not have to be synchronous with the conversion clock, you would just need to read all four devices fast enough that you were finished before the next DATA_AV - you can see this concept in Figure 31 of the THS1206 datasheet.

Hello Tom,

lets's assume we use the adress decoder you mentioned before and the adressing is working just fine.  Does the parallel interface really work with only one bus for four ADCs and more? I was told that if one ADC wants to send, the others' output pins need to have a high impedance, or the ADCs need to be in the sleeping mode.

Additionally to that, in figure 7 of "Designing With the THS1206 High-Speed Data Converter" (found in the Application notes) the Data of BINM is still available on the data output pins, until the next DATA_AV is activ. Does this occupy the data bus and hinder other ADCs from sending their data?

I made a schematic how i want the reading to be done. It shows the reading pattern. Can you please tell me if this is the right way of reading the data?

Reading pattern.pdf