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Original question:

ADC12DJ3200EVM: Data corruption in normal mode

ADC12DJ3200EVM: Can't get KCU105 firmware to work

Robert Stalker
Prodigy 85 points
Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: ADC12DJ3200, LMK04828

Hi,

I have a ADC12DJ3200EVM Rev A board connected to a KCU105 board.  I downloaded the KCU105 reference design firmware.  I followed the instructions in the "KCU105 ADC12DJxx00 JESD REFERENCE DESIGN USER GUIDE".  I set the FMC Vadj voltage to 1.8V.  Use the ADC GUI to config to clk source = on-board, Fs = 1500 Msps, Mode = JMODE0 and programmed the TI board.  Set JESD204B to scrambler enabled, K=4, sync input = SYNCSE, JESD Test mode = ramp, pre-emph = 0.  I then load the provided *.bit and *.ltx files into the Vivado hardware debugger GUI (2016.1).  The FPGA programs correctly and I can see all debug signals in waveform window.  I then do an immediate trigger capture and all signals are 0.  Sync stays low at 0.  I can see LED 4 (clock) blinking indicating it's getting a reference clock.  RX VALID always stays low.  It seems like some basic parameter isn't set right.


I was able to put an IBERT image into the KCU105 board, changed TI ADC test mode to PRBS23, and verified the QPLL locks and performed eye scans.  Eyes look good.  BER rate is about 1E-14.  So, it seems like signal integrity is OK.

Is there a "trick" to getting the KCU105 firmware to work?  Something not mentioned in the user guide?


It seems like I'm missing something very basic.  Presumably this bitfile has been tested and validated on the same hardware.  Do I need to worry about the KCU105 PCB versions?

thanks in advance for any help and advice!

  • 0
    Prodigy 85 points
    Also, I should mention that the firmware I downloaded and attempted to use is at this link:
    www.ti.com/.../slvc698

    I noticed there is a different KCU105 firmware for use with the HSDC Pro software and it was designed using Vivado 2016.3. I'll download this firmware and try it to see if it works for me.
  • 0
    TI__Intellectual 2750 points
    Hello Robert,
    Xilinx usually has a changelog in their 'design files' that is published but this board does not have it.
    I did find an answer record here www.xilinx.com/.../66418.html

    It looks like they upgraded the speed grade of the SI clock device to support a higher frequency range, but this should not change the reference design. I did not notice any other changes that would explain the issue.

    I have forwarded the question to an engineer that works with the ADC12DJ3200

    Regards,
    Brian
  • 0 in reply to Robert Stalker
    Prodigy 85 points
    In the HSDC Pro user guide, it has a section called "DAC and ADC GUI Configuration File Changes When Using a Xilinx® Development
    Platform". Does the EVM GUI software have to be patched in order to work with Xilinx KCU105 boards?
  • 0 in reply to Robert Stalker
    TI__Guru* 91947 points

    Robert,

    I got this running with our hardware following the start up guide attached. Please give this a try along with the attached bit file. This should be the same file that comes with HSDC Pro. If this does not work, let me know the status of the LED's on both boards.

    Regards,

    Jim

    KCU105.zipKCU105_ADC12DJ3200_JMODE0.pptx

  • 0 in reply to Robert Stalker
    TI__Guru* 91947 points

    Robert,

    In some cases, the GUI config file has to be changed slightly. This is usually just a clock enable and or divider value. This was true for the VC707, KC705 and ZC706 but not for the KCU105.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 85 points
    I followed your instructions and it works! I was able to perform a capture at 4G sample rate. LED 0 is solid green, LED 4 is flashing.

    I assume the bitfile you provided corresponds to the firmware at this link, as opposed to the other firmware at the link in previous post.
    www.xilinx.com/member/jesd204_eval/uhwd_2016_3_v1_0.zip

    The new firmware works with vivado 2016.3, whereas the older version is based on 2016.1.

    The PPT mentions that "When lane rate is less than 3.9G, the GUI will not change the divider to match the core FPGA clock. The FPGA will require a separate clock input for REFCLK and Core clock." Does this mean the firmware needs to change for lower sample rates?
  • 0 in reply to Robert Stalker
    TI__Guru* 91947 points

    Robert,

    When the line rate falls below this value, the firmware will still work. It just requires a different ref clk frequency than what the ADC GUI thinks it should use. After you enter a new ADC output data rate in the GUI, a new window opens that shows what JESD reference clock frequency from the EVM is needed by the KCU105. The user then has to go the LMK04828 Clock Output tab of the ADC GUI, and make sure the divider for this clock is set correctly. In the case when a 1.6G data rate is selected, the DCLK divider has to change from the default value of 10 to 5 for this line rate to work. The same firmware is always used.

    Regards,

    Jim  

  • 0 in reply to jim s
    Prodigy 85 points
    Does this DCLK divider control the JESD REF clock or the core/glbl clock? or both?
    What is the Fs to Fref ratio when changing from 10 to 5? is that effectively changing it from the normal 20:1 to 10:1?
  • 0 in reply to Robert Stalker
    TI__Guru* 91947 points

    Robert,

    DCLK0 controls the REF clock and DCLK12 controls the core clock if both clocks are being used by the firmware. The 10:5 changes the LMK VCO divider from 10 to 5 so this is actually a multiply by 2 end result.

    Regards,

    Jim