DAC38RF82EVM: Alarms in DAC38RF82EVM GUI, DAC lane read_error and read_error

Hello Eben,
 
Sorry for the delay.

We now observed the behavior that after toggling (setting and resetting) Bit 12 (SRDS_FIFO_ALM_CLR)
of JESD FIFO Control Register (0x0D) the above errors disappear. It looks like they are cleared and do not rise again.
 
We do have following configuration. We have two DACs on the PCB. One with 4 lanes and one with 8 lanes  connected to the FPGA.
Both are supplied with 9 GHz External Differential Clock. DAC PLL is not used.

DAC 0 Settings:
L-M-F-S-Hd = 84111 ; 2 TX; 1 IQ pair per DAC; Interpolation 18; Input Rate max 500 MSPS; fDAC  9 GSPS
Current Serdes Lane Rate =5000.00MHz
Maximum sample rate for Dual DAC,1 IQ pair,4 Lanes,18x interpolation is 9000
Serdes Configured to Half Rate; Serdes clock predivider = 4; Serdes PLL Vrange = 0; Serdes PLL Multiplier = 10

DAC 1 Settings:
L-M-F-S-Hd = 44210 ; 2 TX;  1 IQ pair per DAC; Interpolation 18; Input Rate max 500 MSPS; fDAC  9 GSPS
Current Serdes Lane Rate =10000.00MHz
Maximum sample rate for Dual DAC,1 IQ pair,2 Lanes,18x interpolation is 9000
Serdes Configured to Full Rate; Serdes clock predivider = 4; Serdes PLL Vrange = 0; Serdes PLL Multiplier = 10

We do nearly follow the start up sequence mentioned in the datasheet.
The difference is, that after the complete DAC startup sequence we do initialize the FPGA jesd core.
And then again we do clear all DAC alarms.

DAC 0 active alarms after Startup Sequence followed by FPGA JESD-Core initialization

Loss of signal alarm for lane 0
Loss of signal alarm for lane 1
Loss of signal alarm for lane 2
Loss of signal alarm for lane 3
Loss of signal alarm for lane 4
Loss of signal alarm for lane 5
Loss of signal alarm for lane 6
Loss of signal alarm for lane 7
PLL alarm for SERDES block 0
PLL alarm for SERDES block 1
CHA Lane 0 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 0 8b/10b disparity error
CHA Lane 0 8b/10b not-in-table code error
CHA Lane 0 Code synchronization error
CHA Lane 1 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 1 8b/10b disparity error
CHA Lane 1 8b/10b not-in-table code error
CHA Lane 1 Code synchronization error
CHA Lane 2 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 2 8b/10b disparity error
CHA Lane 2 8b/10b not-in-table code error
CHA Lane 2 Code synchronization error
CHA Lane 3 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 3 8b/10b disparity error
CHA Lane 3 8b/10b not-in-table code error
CHA Lane 3 Code synchronization error
CHB Lane 4 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 4 8b/10b disparity error
CHB Lane 4 8b/10b not-in-table code error
CHB Lane 4 Code synchronization error
CHB Lane 5 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 5 8b/10b disparity error
CHB Lane 5 8b/10b not-in-table code error
CHB Lane 5 Code synchronization error
CHB Lane 6 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 6 8b/10b disparity error
CHB Lane 6 8b/10b not-in-table code error
CHB Lane 6 Code synchronization error
CHB Lane 7 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 7 8b/10b disparity error
CHB Lane 7 8b/10b not-in-table code error
CHB Lane 7 Code synchronization error

Then after clearing the DAC 0 Alarms following alarms are active
Clearing = Clear all DAC alarms: Write 0x0000 to alarm registers on Page0: 0x04, 0x05 and Page1/2: 0x64 to 0x6D

CHA Lane 0 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 1 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 2 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 3 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 4 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 5 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 6 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 7 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)

DAC 1 active alarms after Startup Sequence followed by FPGA JESD- Core initialization

Loss of signal alarm for lane 1
Loss of signal alarm for lane 2
Loss of signal alarm for lane 5
Loss of signal alarm for lane 6
PLL alarm for SERDES block 0
PLL alarm for SERDES block 1
CHA Lane 1 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 1 8b/10b disparity error
CHA Lane 1 8b/10b not-in-table code error
CHA Lane 1 Code synchronization error
CHA Lane 6 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 6 8b/10b disparity error
CHA Lane 6 8b/10b not-in-table code error
CHA Lane 6 Code synchronization error
CHA Alarm caused when the sysref is placed at an incorrect location.
CHA Asserted if the clkdiv144 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv128 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv72 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv36 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv32 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv24 in the CDRV_SER shift register is all zeros. (Connected to the div18 port)
CHA Asserted if the clkdiv16 in the CDRV_SER shift register is all zeros.
CHA Asserted if the clkdiv8 in the CDRV_SER shift register is all zeros.
CHB Lane 2 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 2 8b/10b disparity error
CHB Lane 2 8b/10b not-in-table code error
CHB Lane 2 Code synchronization error
CHB Lane 5 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 5 8b/10b disparity error
CHB Lane 5 8b/10b not-in-table code error
CHB Lane 5 Code synchronization error
CHB Alarm caused when the sysref is placed at an incorrect location.
CHB Asserted if the clkdiv144 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv128 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv72 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv36 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv32 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv24 in the CDRV_SER shift register is all zeros. (Connected to the div18 port)
CHB Asserted if the clkdiv16 in the CDRV_SER shift register is all zeros.
CHB Asserted if the clkdiv8 in the CDRV_SER shift register is all zeros.

Then after clearing the DAC 1 Alarms following alarms are active
Clearing = Clear all DAC alarms: Write 0x0000 to alarm registers on Page0: 0x04, 0x05 and Page1/2: 0x64 to 0x6D

CHA Lane 1 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHA Lane 6 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 2 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)
CHB Lane 5 Read error: High if read request with empty FIFO (Note: only released when JESD block is initialize with mem_init_state)

Best regards
Christoph