ADS54J54: How to config EVM if I want to evaluate the ADS54J54 ADC performance when using external Sampling clock?

User,

What frequency do you plan on using for the ADC? Depending on this value will determine how the LMK is used. If you can derive the SYSREF and TSW14J56 reference clock with the on-board VCO, then you only need to send the 10MHz reference output from the ADS54J54EVM (SMA J16) to the external reference input of your signal generator used for the ADC clock. You can do this the other way as well (send a 10MHz from the signal generator to J14 of the EVM).  If the frequency cannot be created from the VCO, then you must provide another external clock source to SMA J7 to be used by the LMK. This source must be synchronized with the ADC clock source.  You then will use the LMK in clock distribution mode to generate the required clocks.

Regards,

Jim   

Jim,

Many thanks for your reply.

The frequency plan for the ADC: sampling rate is 500MSps(without 2X decimation), the clock to TSW14J56 is 250MHz and 1.5625MHz.

I set up the test bench as following figure: using external 500M clock as ADC sampling clock.

Under the test bench, I can successfully capture the data, but the connection becomes very unstable: sometimes can capture, sometimes fail to capture.

So is there any other settings I maybe omitted? such as SYSREF CLOCKs?

Best regards,

Xiaobo

User,

What value are you using for K? What is your LMFS settings? How much current can your power supplies provide to these two EVM's? Are both LMK PLL lock LED's on after the LMK is configured?

Regards,

Jim

Hi Jim,

Today, I set up the environment again almost the same as yesterday, and find the connection becomes very stable. LMK PLL lock LEDs are on normally.

So I think the connection unstable is not a real problem. Sorry for the confusion.

Thanks very much.

Best regards.

Xiaobo