Original question:
Let me try to clear up the confusion.
A sample is one conversion, also could be referred to as a conversion cycle, or one conversion result.
For the ADS8691, Figure1 shows one sample, or, in other words, one conversion cycle, with a time span of t_cycle. The datasheet defines this as a minimum of 1 us. This is where the 1 MSPS comes from, you can get one million samples, AKA conversion results, in one second.
As for the bits, this is something different, and does not necessarily directly connect to the 1MSPS.
Note, in the above picture, the t_cycle, the conversion cycle is divided, this is where the t_conv of 665ns is located, which is part of one conversion cycle.
During the data read time is when the bits are transferred, as shown in the figure3 in the datasheet. The output bits follow the SCLK frequency and must be all outputted during the allotted Data Read time, which can be seen is shorter than the t_cycle time.
Thus when you read a sampling rate, this does not refer to the bit output rate.
You will need to check the datasheet based on what interface you are using to be sure to use the correct timing requirements.
There is alot of material available one being TI Precision labs, which is very helpful. I would definitely recommend this as you progress with your design, Section5- SAR ADC Input Drive Design will prove most helpful, I think. Also, TI's Data Converter Learning Center has good information in an overview label broken down into parts, including ADCs.
Hope this helps, Cynthia
