ADC12DJ3200: JMODE0, Data Format~

4048.TSW14j56_MC firmware design document.pdfXuan,

Not sure exactly what you are asking for  but take a look at the attached document and let us know if this helps.

Regards,

Jim

Dear Jim:

   Thank you for your document first, but unlucky,I am not interested in it.

   I want to know ,when I got the data of 512 bits,How can I divided it into 40 groups ,according to the table 21 of the datasheet  .

   for example : s0=data[31:20];s8=data[19:8];s16={data[7:0],data[287:283]}...

  I think there is sth. wrong with the table 21. 

  thank you.

   Best wished.

                      xuan

Hi xuan
Can you share any screen pictures or tables showing the data you are receiving in the FPGA?
It would be best if you could capture data with the JTEST Test Pattern mode set to Transport Layer test mode (Register 0x205 = 0x05).
Are you using Xilinx or Intel/Altera FPGA to receive the JESD204B data?
Are you using the FPGA vendor JESD204B IP as a starting point or are you designing your own JESD204B receive firmware yourself?

Best regards,

Jim B