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DAC38J84EVM: RPAT and JSPAT pattern verification

Yogitha Rajasekhar
Intellectual 290 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828, DAC38J84, ADS42JB49

Hi,

I want to test the JESD link between KC705 and DAC38J84EVM. I have enabled RPAT pattern generator in my JESD tx design. In the DAC datasheet it is mentioned that RPAT and JSPAT patterns can be verified using error counters.

Where are these counters visible? 

Is there any register configuration required to enable RPAT verification? Is this test enough to verify complete JESD link?

Thanks,

Yogitha 

  • 0
    TI__Guru 72269 points

    Yogitha,

    You will need to set the following registers to enable either the RPAT or JSPAT for the link layer testing:

    the test result for each lane is reflected for the lane status alarm. you will need to clear the alarm accordingly

  • 0 in reply to Kang Hsia
    Intellectual 290 points

    Hi Kang Hsia,

    The JESD tx from Xilinx has the following register configuration for test mode selection. 

     

    The config74 register has enable for D/K/ILA sequence. Does this mean RPAT and JSPAT need not be enabled in the receiver? And the test result can still be verified in config100 register?

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    Intellectual 290 points

    I have one more question. I have followed below steps to verify test patterns

    I have programmed FPGA to transmit K/D characters

    Configured DAC in LMF_148  x4 and input rate of 61.44 MSPS > Program LMK04828 and DAC3XJ8X 

    Set the DCLK divider of clk out0 to 12 and clk out12 to 24 (FPGA reference clk and global clk)

    In Serdes and Lane Configuration Enable RX0

    set config74 [7:6] to 10 / 01

    Reset DAC > Trigger LMK 

    Read Config100. The Lane0 FIFO error flag is set.

    Did I miss any step in the DAC configuration for testing through patterns

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru 72269 points
    Yogitha,

    The link layer testing on the DAC38J84 does not support RPAT, JSPAT, and PRBS. These are optional testing per the JESD204B standard and we did not include them.

    You have the basic testing configuration correctly. You will basically need to configure the entire DAC as is per your applications need. You then need to enable the JEST_TEST_SEQ in the register per the test that you want to do. For instance, if you want to test K28.5, then you will need to configure your FPGA with K28.5 test while programming the JESD_TEST_SEQ to be b10. Besides reading back the confgi100 reigster, you will need to clear the register by writing 0x00 first, before reading to get the latest status.

    -Kang
  • 0 in reply to Kang Hsia
    Intellectual 290 points

    Hi Kang,

    My JESD TX in the FPGA is configured with 1 lane and 4Gbps serdes line rate. What should be the DAC input data rate for this configuration. If I take LMF as 148 it comes around 50MSPS of input data rate. Is this the valid calculation? Which of the four output channels (A/B/C/D) will have the valid output? Is there an option to disable three DACs and use only one DAC channel. In this case does the M value change to 1?

    In the DAC38J84EVM tool, with on board clocking option there are only fixed number of data rate selection. If I have to use external clock are there any recommendations or specifications for the clock source (freq range/jitter/noise etc.,) 

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru 72269 points

    Hi Yogitha,

    Your calculation is correct. The input data rate from the baseband data will be 50MSPS per I or Q stream to each of the DAC. You may use the GUI to calculate the necessary parameters

    Since this is 14810 mode, the single SERDES lane contains aggregated data for all four DACs, hence, you will need to send data to all four DACs. We don't really have a nice/clean way to send only data to one DAC. You may need to look into 4 lanes modes where each lane contains data for a DAC. However, the JESD state machine for the SYNC response (JESD RX SYNC response) may need to be tuned to ignore three other DACs. I think the configuration may be a bit messy.

    In terms of clock quality, look for these two app notes:

  • 0 in reply to Kang Hsia
    Intellectual 290 points

    Hi,

    In LMF_148 mode, if all 4DACs will be used, which of the 4 output channels (A/B/C/D) will have the valid output. 

    Below is my DAC configuration

    I have configured my JESD tx to transmit K characters and I see the 8b/10b disparity error, FIFO write error, DAC clk out of lock and PLL1 out of lock alarm is set. What does this imply?

    Also, what is the significance of bus width under SERDES and Lane configuration section. When I change it to 20 bit, I see FIFO Read empty and FIFO Read error alarms also set.

    I have probed sysref and sync on FPGA side and I could see that sysref is captured and sync is de-asserted. Does this confirm that JESD link is initialized? 

    Do you have any specific clock source recommendation for DAC38J84. This external clock source should also generate sysref and FPGA clk?  

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru 72269 points
    Hi Yogitha,
    In 14810 mode, all four DACs are configured to be functional.

    In 14810 mode you have above, you are not using on-chip PLL, therefore DACCLK out of lock (i.e. PLL/VCO circuit) is expected. Also, since you are only using 1 lane, only SERDES core 0 is used. Therefore, SERDES core 1 out of lock is also expected.

    For the FIFO write error and 8b/10b disparity error, could you please try to clear the alarm and read. You need to actually measured the SERDES line coming out of your FPGA to make sure they are active. Otherwise these errors are expected

    Please use the default bit width for the verified JESD and SERDES mode.

    SYNCB should toggled from HI-Low-HI transition to indicate the sync request is no longer needed. The fact that you are seeing 8b/10b error could indicate that at one time the SYNC could be toggled low but your FPGA did not register it. You can always toggle "RESET JESD core at the front page to see if you can see the HI->LOW->HI transition again.

    I want to clarify some confusion. The use of external clock in this case is to provide flexibility in clock frequencies. The on-board LMK04828 is basically a buffer to properly source the DACCLK and also divide down properly the associated SYSREF to the DAC. In actual implementation, the on-board clock source is the one we recommended already, which is the LMK04828 that you can use in your design. If you want to configure the LMK04828 in bypass buffer mode, then you will need to feed in an external signal generator. As mentioned before, the LMK in bypass buffer mode will do the appropriate divide operation for DACCLK and SYSREF frequencies needed.

    -Kang
  • 0 in reply to Kang Hsia
    Intellectual 290 points

    Hi Kang,

    Thanks for the support. I could see HIGH -LOW - HIGH transition on SYNC~ signal.

    I performed test pattern verification using K/D characters and I do not see any alarm going high. But when I transmit ILA sequence I see that Elastic Buffer Overflow alarm set and the SYNC signal is always toggling. What could be the possible reason for this error.

    Also, when I transmit PRBS pattern, where should I check the TESTFAIL condition.

    Regards,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru 72269 points

    Yogitha,

    for the ILAs, there are lane IDs that you have to program on both the FPGA and DAC in order for the ILAS to pass. See attached for detail. Each lane has specific lane ID.

    The test fail condition can be routed out to the CMOS alarm pin with the programming of DTEST bits.

    5531.DAC3xJ8x ILA Sequence.xlsx

  • 0 in reply to Kang Hsia
    Intellectual 290 points

    Hi Kang,

    I need some inputs on the below 

    My complete setup consists of  ADS42JB49 EVM + TSW14J10 + KC705 and KC705 + DAC38J84 EVM. ADC/DAC is connected to two KC705 through FMC and two KC705 are connected. I want to verify the DAC ouput against the ADC input.

    Input to ADC is 5-65MHz RF signal on single channel and JESD interface is configured for 2 lane, 4Gbps line rate. In DAC38J84 EVM for serdes line rate of 4Gbps, I need an external clock of 100MHz. By any way can I generate this clock from ADS42JB49 EVM? 

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    You can get a 100MHz clock out of the ADS42JB49 using SMA's J10/J15. This is CLKOUT6_P/M from the LMK. What do you plan on doing with this clock?

    Regards,

    Jim

    6685.ADS42JB69EVM-SCH_D.pdf

  • 0 in reply to jim s
    Intellectual 290 points
    Hi Jim,

    My question was if I can generate clock from ADC and use that as an external reference clock for the DAC? Since DAC onboard clock does not support 4Gbps line rate

    Thanks,
    Yogitha
  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    What sample rate, interpolation rate and LMFS settings do you plan on using for the DAC?  I will need this other information to answer your question. The clock can only come from the LMK as the ADC does not have an output clock you can use. Why are you so concerned about a 4Gspb serdes rate?

    Regards,

    Jim 

  • 0 in reply to jim s
    Intellectual 290 points

    Hi Jim,

    On the ADS42JB49 EVM, there is an clock output from LMK i.e., Clok out6 (SMA output). Can I program this as 100MHz and use this as external clock for DAC EVM. 4Gbps serdes rate, sampling rate of 200MSPS and 1 lane at DAC is my requirement. Based on that LMF_148 and interpolation x4 . 

    Was it right choice to connect ADS42JB49 and DAC38J84 with 2 serdes lane on ADC and 1 serdes lane on DAC? Or should I had to use any dual/single channel DAC

    Thanks,

    Yogitha

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    Yes, you can program Clock Out 6 to be 100MHz. You will setup the LMK PLL2 to use VCO1 at 3000MHz and divided CLK Out 6 by 30. Set this output to LVPECL 2000mV for maximum swing. Make sure the two SMA cables you use to connect the two clock signals between the boards are the same length and as short as possible to minimize signal loss.

    The number of serdes lanes you selected is fine. This is a valid setting for the DAC as shown in attached screen shot from the DAC GUI.

    Regards,

    Jim

    LMFS_1481.pptx

  • 0 in reply to jim s
    Intellectual 290 points

    Hi,

    I couldn't resolve the Elastic buffer error when testing the ILA pattern. I have cross checked the Lane IDs too. Also during K characters pattern test I get FIFO Read error, Code group Sync error, elastic buffer overflow error and 8b/10b disparity error. In both the cases sync signal is always toggling.

    I have attached my DAC configuration file. Can some help on this.

    Thanks,

    YogithaDAC38j84_148.cfg

  • 0 in reply to Yogitha Rajasekhar
    TI__Guru* 91947 points

    Yogitha,

    For some reason, your config file has over 16 register settings different than what I sent you. I tested our setup with your settings and enabled DCLKout 6 to be 100MHz with the file attached. Please use this and do not make any changes.

    Regards,

    Jim

    GUI_DAC38j84_148.cfg