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Original question:

TVP5158 EMI Emission Problem

TVP5158: TVP5158 EMI Emission Problem

kartik gandhi
Prodigy 250 points
Part Number: TVP5158

Is there any setting available withing TVP5158 to reduce rise time of CLOKOUT Pin.

We are using two TVP5158 and cascading mode and using single crystal part# FH2700019Z (Pericom) to feed 1st TVP5158.

Taking CLKOUT from 1st TVP5158 and feeding to 2nd one as input source clock.

We are also taking two 8-bits parallel output from each TVP5158 which is running @ 108MHz.  

During FCC testing, we have observed that it is radiating at 27MHz, 108MHz, 379.9MHz,  

Is there any setting posibsle withing TVP5158 to control its rise time of output PCLK and CLKOUT signals to reduce its rise time?

-Kartik

  • 0
    TI__Mastermind 43875 points

    Unfortunately there are no setting to change the rise/fall times.

    Often the rise/fall time is actually not the culprit for emissions since emissions from rise/fall times will introduce harmonics at the rise/fall rate, and not actually at the clock frequency itself.

    When there are frequencies at the clock rates it is more often due to bad/incomplete ground returns which cause inductive loops, hence antennae.

    Make sure that you have a solid, uninterrupted ground plane for the entire lengths of all clock/data signals and that they are connected to all source/sink nodes.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 250 points
    Hi Steve,

    Thanks for quick reply but I am currently in final certification stage and design is passing but with very low margin from limit line.

    Is it necessary to connect XTAL_REF(pin 100) of TVP5158 through 0E resistor to VSSA? TVP5158 datasheet says that pin 100 is internally connected to analog ground. EMI results shows improvement after disconnecting pin 100 from analog ground.

    BR,
    Kartik
  • 0 in reply to kartik gandhi
    TI__Mastermind 43875 points
    Kartik,
    I don't believe it is necessary, but the fact that it makes a measurable difference implies that there is fundamentally a grounding/ground loop issue.

    Is the connection to ground (after the 0R resistor) a direct connection to your ground plane, or is there a long trace/path before it is able to punch to your ground plane (hence a loop)?

    I assume you do have a good, solid ground plane and all vias to it are as close as possible to the devices? If not, then you might want to consider making ground layout changes if you ever have cause to make updates/changes to your design.

    Do you have a single ground plane or separate analog and digital planes? If separate can you try connecting them together in as many places as possible? I myself have made a mess of ground return paths by trying to split them and have found that in most cases, if you are careful with signal routing you can actually get better results from a single plane. Obviously there are many scenarios where this is not true, but with the frequencies involved here split planes can cause more harm than good if not fully characterized.

    Making sure signal paths and return loops are minimized is critical to reducing EMI, and don't forget that the return current will try to follow the source signal, so there can be no breaks or gaps in the ground return path under the signal trace.

    BR,
    Steve