ADS4449: CLOCK INPUT LEVEL FOR LVPECL

LOKESWARA REDDY M

Part Number: ADS4449

HI,

I am using ADS4449 in my design. I have a concern about the clock enter into ADC. if LVPECL clock with Vpp(.636v or 0dbm) entering into ADC what is its impact on DYNAMIC RANGE and ADC is able to do its operation with this clock.

REGARDS

M LOKESWARA REDDY

BEL

080-22195851

over 5 years ago

0 jim s over 5 years ago

TI__Guru* 91947 points

Reddy,

The amplitude will effect SNR and SFDR of the ADC. See Figure 26 of the data sheet.

Regards,

Jim

0 LOKESWARA REDDY M over 5 years ago in reply to jim s

Prodigy 80 points

hi,

If am using 100MBPS sampling rate and input frequency 70MHZ and 0dbm clock( lvpecl )what will its impact on SNR and SFDR .where I will get information?If I use lvds clock with the above specifications any improvement in SNR and SFDR?

REGARDS,

M lokeswara reddy

Bel

0 jim s over 5 years ago in reply to LOKESWARA REDDY M

TI__Guru* 91947 points

Bel,

Since the performance of SFDR and SNR are pretty constant with a clock amplitude between 0.5 - 1.7 Vpp, after looking at Figures 34 and 36, I would estimate your SNR to be around 70 dBFs and SFDR to be around 87 dBc with your settings. You would probably get slightly better numbers with your clock amplitude between 1.4 - 1.7 Vpp.

Regards,

Jim

0 LOKESWARA REDDY M over 5 years ago in reply to jim s

Prodigy 80 points

hi,

REGARDS,

M lokeswara reddy

Bel

0 jim s over 5 years ago in reply to LOKESWARA REDDY M

TI__Guru* 91947 points

Reddy,

I did some tests with our EVM using a 100MHz input clock that varied from 0.421Vpp to 1.12Vpp with a 70MHz analog input tone. The SNR and SFDR results are shown in the attached file. Hope this helps with your question.

Regards,

Jim

ADS4449EVM Test.pptx

0 LOKESWARA REDDY M over 5 years ago in reply to jim s

Prodigy 80 points

jim,

thank you for your reply.

regards,

M LOKESWARA REDDY

BEL

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ADS4449: CLOCK INPUT LEVEL FOR LVPECL