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DAC38RF82: PLL Unlock Alarm

KAEDE KUDO
Expert 2700 points
Part Number: DAC38RF82

Hello,

I have a question about PLL Unlock Alarm of DAC38RF82.

(PLL Unlock Alarm = Add 0x05 bit 0)

1. Could you tell me the way to Mask the PLL Unlock Alarm?

2. Is the PLL Unlock Alarm being asserted when bypassing Internal PLL?

Best Regards,

Kaede Kudo

  • 0
    TI__Expert 4880 points
    Kaede,

    I forwarded your question to the device owner, he should get back to you shortly.

    yusuf
  • 0 in reply to Yusuf%20Agoro
    Expert 2700 points

    Hello Yusuf-san,

    Thank you for your comment.

    I'll wait his feedback.

    Best Regards,

    Kaede Kudo

  • 0
    TI__Guru* 91947 points

    Kaede,

    There is no mask for this. If internal PLL is bypassed, this alarm still gets set.

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 2700 points

    Jim-san,

    Thanks for your answer.
    And, I'm sorry for my late reply.
    I understood your comment.

    I have something I want to ask you a little more.

    [Q]

    Does the output disappear when the internal PLL is Bypassing and PLL Unlock Error is issued?
    There is no error other than PLL Unlock error.

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    TI__Guru* 91947 points

    DAC38RF82_NCO_CW.pptxKaede,

    The output should not disappear. Can you enable just the NCO to see if you get a valid output? Follow the instructions attached for this test.

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 2700 points

    Hello Jim-san,

    Thank you for your fast reply!

    We confirmed the output at below test.

    Quick Start - DAC RESETB Pin Toggle

    Quick Start - Load Default Click

    Low Level Vi - Open Config - (attached file)

    181009_DAC38RF82_Test Config.cfg

    Digital(DAC A) - Mixer Path AB enable

    Digital(DAC A) - NCO Path AB enable

    Digital(DAC A) - NCO Sampling=4000, NCO=1000, Phase=0 ⇒ Update NCO

    Digital(DAC A) - Constant Input enable, Constant Value=3FFF

    Digital(DAC A) - Output sum selector - Add Path AB  

    Digital(DAC A) - Output sum selector - Add Path AB sample (adjacent)

    Digital(DAC B) - Mixer Path AB enable

    Digital(DAC B) - NCO Path AB enable

    Digital(DAC B) - NCO Sampling=4000, NCO=1000, Phase=0 ⇒ Update NCO

    Digital(DAC B) - Constant Input enable, Constant Value=3FFF

    Digital(DAC B) - Output sum selector - Add Path AB  

    Digital(DAC B) - Output sum selector - Add Path AB sample (adjacent)

    And our customer confirmed the output With a similar test.

    But, PLL Unlock Alarm is observed.

    (They are using not EVM but original board)

    But, If you change the following from the above procedure, you will not be able to check the output.

    - Constant Input = disable

    - Constant Input from FPGA

    At this time, the only observed alarm is PLL Unlock Alarm.

    So, we believe there is no mistake in setting up Serdes Lane and JESD.

    I thought that the reason for not outputting was PLL Unlock Alarm, but I understood what is not so in your comment.

    Is there any other setting that affects the presence or absence of output?

    Thank you for your cooperation.

    Best Regards,

    Kaede Kudo

  • 0 in reply to KAEDE KUDO
    TI__Guru* 91947 points

    Kaede,

    To help me trouble shoot this, please provide the following information:

    1. DAC sample rate

    2. Interpolation factor

    3. LMFS settings

    4. K setting

    5 SYSREF frequency

    6.Number of IQ pairs or real data input

    Regards,

    Jim 

      

  • 0 in reply to jim s
    Expert 2700 points

    Hello Jim-san,

    Thank you for your reply.

    1. DAC sample rate = 4G

    2. Interpolation factor = x2

    3. LMFS settings = 8212

    4. K setting = 32

    5 SYSREF frequency = 3.125MHz

    6.Number of IQ pairs or real data input = 2

    Best Regards,

    Kaede

  • 0 in reply to KAEDE KUDO
    Expert 2700 points

    Hello Jim-san,

    I visited customers.
    I found that the setting of the FPGA used by the customer was not properly done.
    There is no feedback that customers have output yet, but we will close this Thread.

    Thank you for your strong support！

    Best Regards,

    Kaede Kudo