ADC128S102: ADC128S102 reading problem when switching between channels

Hi John,

As Mr. Domanski noted in the original post, the internal sample cap does not automatically discharge in the ADC128S102 between samples.  If you are having similar problems to those expressed by Mr. Song, you can follow the same advice provided in the original post.  There are also a series of TI Precision Labs dedicated to ADC's which you might find useful.  One in particular is SAR ADC Input Driver Design which goes through the basics of the sampling mechanism of a successive approximation register ADC.

Hi John,

I see that you didn't like my answer, or at least it did not resolve your question, so lets try something else. In general, there are three options for the sampling cap on the inside of a SAR converter, the designer could short the cap to GND between samples, he or she could short the cap to the reference voltage, or they could do nothing and just leave the last sampled voltage remain. This is where the description from Mr. Domanski was coming from, the ADC128S102 does not internally discharge the sampling capacitor - it holds the last value which means the input drive circuitry has to settle the new values on the cap while its in hold mode. Technically, there is no discharge phase on the sampling cap, so there is no minimum time to provide you. What sort of problem are you trying to resolve?

Hi Tom. Thanks for the response. Lab experiments I have been running on my design reveal a similar result as the one described in "ADC128S102 reading problem when switching between channels". Mr. Domanski's response implies that there is some unspecified timing constraint that limits the rate at which the user can change from one channel to the next. Am I misunderstanding?

Regards,
John

Hi John,

Sorry for the confusion. It's not an 'unspecified' timing thing really, it's having the ability to charge the sampling cap in specified acquisition time of the ADC, which happens to be the first three SCLK cycles (see tACQ on page 7) with the ADC128S102. At the maximum SCLK speed of 16 MHz, that gives you 187.5 ns in which you need to have your input settled on the input cap. This normally means you need to have a low impedance source and potentially a buffer ahead of the mux as depicted in Figure 38. If you go back to the original post, you might notice that Geraldo slowed down the SCLK frequency and saw improvements in the conversion results. This makes sense when you consider that using the slowest SCLK (8 MHz) you now have 375 ns to settle the inputs. Much of this (from a general SAR ADC standpoint) is explained in detail in the TI Precision Labs material I pointed you too.

Hi John,

Have you made any headway here? Feel free to share the ADC128S102 input section of your schematic with us if you want suggestions on how to improve channel switching/input settling issues.