ADC12J4000EVM: ADC and LMK configuration

ADC12J4000EVM, ADC12J4000

I think I found the answer to my question #1

Jim's answer: We used M = 8 (8 ADCs) so that the samples can be ordered with earliest samples transmitted first while complying with the sample ordering rules of the JESD204B standard. Lane 0 has the samples for converter 0, lane 1 for converter 1 and so on. From a user standpoint, this converter is really an M=1 (single ADC) device

Regarding my question number 4. I think Table 13 is the answer but I don't think that I understand it correctly.

Xilinx's datasheet (pg066-jesd204.pdf) for the JESD IP core says that "The AXI data input and output by the core contains four bytes

per clock cycle per lane with the least significant byte position in each 32-bit block holding the first byte received from the ADC or transmitted to the DAC"

So I have 256bits output bus (8 lanes, each 32bits). According to Table 13 (ADC datasheet)

Per clock cycle I will have 16 full samples (S0-S15) and 8 not full samples (S16-S23).  Am I right?

I still cannot figure out how lane rate is supposed to be 8gsps in 4gsps sampling bypass mode? Could anyone please explain?

And question #3 is also not clear for me.

I am going to connect EVM board directly to the VC707. 
Will the configuration settings for the adc,lmk and trf in my first post work in my case?

Provided clocks from the evm will be 
Refclk = 400MHz
Coreclk = 200MHz

as per the doc you pointed to me. Right?

Tnaks in advance,

-Dmitri

Hi Dmitri

The lane rate calculation is more complicated because the N value for DDC Bypass mode is 12 instead of 16, and because of the 4 tail bits at the end of the frame in all lanes.

If we used that same equation with N=12 we would have:

LANE_RATE = M * N * 1.25 * Fs / L = 1 * 12 * 1.25 * 4000 / 8 = 7500Mbps.

Since we have an additional 4 bits to make an even 8 octets per frame, we need to increase the frame rate by that factor.

So we have 7500 Mbps * 64/60 = 8000Mbps.

The CoreCLK and RefCLK frequencies you have calculated are correct for the Xilinx FPGA at 8000 Mbps line rate.

Best regards,

Jim B

Jim, thanks.

Hello Dan, Jim.

Seems like the configuration in this example is for ADC12J4000 rev. A0, while I have rev. E3, which seem to have LMX2581 instead of TRF3765. Could you please provide configuration sequences for rev.E3 (ADC, LMX, LMK and whatever else should be configured on the board) for 4 Gsps bypass mode?

Thanks in advance.

-Dmitri

Hi Dmitri
The Rev E3 board with LMX2581 is limited to a maximum ADC clock frequency of 3.76 GHz, so the maximum sample rate is 3.76 GSPS.
Corresponding FPGA clocks from the evm will be:
Refclk = 376 MHz
Coreclk = 188 MHz
If this sample rate is acceptable I will work on a configuration file/sequence that provides these clock outputs.
Best regards,
Jim B

Jim hi.

Thanks. Now I don't understand the clocking scheme of the EVM.

Why LMX2581 is not programmed? 

I don't have a chance to use GUI. The evm board I have is controlled only through SPI routed to FMC (not FTDI). 

Thanks a lot.

Dmitri.

Hi Jim,

Would you be so kind to provide the LMX configuration to be used with the LMK configuration from your previous reply.

What frequencies are supposed to be at the RFoutA and RFoutB outputs of the LMX?

Thanks in advance,

Dmitri.

Hi Dmitri

If you select On-board clocking, Fs = 3760 MSPS and Bypass Mode; DDR and then click the Program Clocks and ADC button the GUI will be automatically loading the following 3 files:

1. LMK04828_DB1_Fs_3500Msps.cfg (this is the one updated with new divider values for the Xilinx clock requirements)
2. LMX2581_Fs_3760Msps.cfg (this outputs 3760 MHz on RFoutA and 1880 MHz on RFoutB)
3. ADC12J4000_DB1_DDR.cfg

Best regards,

Jim B

Hi Dmitri

When the LMK04828 CLK inputs are used as a reference clock for the PLL the maximum clock frequency is 750 MHz.

When used as FBCLKin or Fin for external VCO mode the maximum frequency is 3100 MHz. When used in distribution mode with PLL2 disabled the maximum input frequency is 3200 MHz.

My earlier note was inaccurate. The clock sent to the LMK04828 on RFoutA is at 1880 MHz. The one sent to the ADC from RFOutB is 3760 MHz. It would be possible to used RFoutA at 376 MHz but then the modified LMK04828 configuration file that I provided earlier would not work. You would need to change the FPGA and SYSREF clock dividers to be smaller by a factor of 1880/376 or 5x smaller.

The file LMX2581_Fs_3760Msps.cfg would not be in that path for the Rev A GUI/board. That path will not have any LMX2581 files, but will have the TRF3765 configuration files instead.

The LMX2581 files should be here for the E3 GUI: C:\Program Files (x86)\Texas Instruments\ADC12J4000EVM GUI\Configuration Files

I have provided the file here for convenience:

LMX2581_Fs_3760Msps.cfg

I hope this is helpful.

Best regards,

Jim B

Hi Jim,

I have programmed the EVM (lmx, lmk, adc) with configuration you provided. The LMX produces 1.56 GHz at both outputs, the LMK produces no clocks. I generated a configuration for the LMX using TICS Pro so that it produces 3.76 GHz at RfOutB and 1.88 GHz at RfOutB and tried tis configuration with your configuration for the LMK, the LMX does produce the expected clock rates, however the LMK doesn't seem to work. I configured status leds to indicate DLD PLL1 and PLL2 and it seems like the PLLs aren't locked. The LMK doesn't output clocks at all. I checked random registers via SPI and the readback data is as expected.

I tried to generate configurations for the LMX and LMK with LMX's RfOutA 376 MHz and RfOutB 3760 MHz, the LMK configuration is supposed to make REFCLK = 376 MHz and CORECLK = 188 MHz out of the input 376 MHz. The LMX does produce 376 MHz, the LMK doesn't generate the clocks.

I attached my LMX and LMK configuration to this message. Would you be so kind to check what is wrong with this config, why it doesn't work.

Thank you in advance.

Best regards,

Dmitri.config.7z

Jim, hello.

I just found the reason why I didn't have any clocks at the LMK outputs. The EVM board  was modified so that the input clock to LMK was from SMA (not from LMX).

I am not sure if what I did is correct. I have programmed the LMK to clock distribution mode. The input 376MHz from LMX - is bypassed in LMK to the output (fpga refclk) and fpga coreclk is 376 divided by 2.

SYSREF is not used.

Maybe you have any recommendations?

Thanks for helping!

Dmitri.

Hi Jim,

I seem to succeed in making the EVM and the VC707 interact.

The ramp test mode seems to work perfectly. Here is what I get from the JESD core in the ramp mode:

cbcac9c8_cbcac9c8_cbcac9c8_cbcac9c8_cbcac9c8_cbcac9c8_cbcac9c8_cbcac9c8
cfcecdcc_cfcecdcc_cfcecdcc_cfcecdcc_cfcecdcc_cfcecdcc_cfcecdcc_cfcecdcc
d3d2d1d0_d3d2d1d0_d3d2d1d0_d3d2d1d0_d3d2d1d0_d3d2d1d0_d3d2d1d0_d3d2d1d0

Same mode, GT output:

Then I programmed the EVM to K28.5 test mode:

I guess the link between the EVM and FPGA is OKAY.

Then I send a 200MHz sine from a vector generator to the VIN input and programmed ADC to normal mode.

Here is GT output:

Here is Jesd demapper output:

I used the demapper that you suggested for "ADC12DJ3200 reference Design 6Gbps JMODE0". Although it doesn't match the mapping of the ADC12J4000, I thought I could be able to figure if there is a periodic signal. Some of the samples do seem to be periodic while others don't. Those that are periodic double the frequency when the generator's frequency is doubled (I tried 100 and 200 MHz).

The GT status rxbyteisaligned_out signals are high while in the ramp mode and low in the normal mode.

ramp mode gt status:

The ADC programming sequence is as follows:

ADC12J4000
0x0021 0x00 // Initiate reset of all registers
0x0021 0x01 // De-assert reset
0x0030 0xC0 // SYSREF receiver and processor ON
0x0040 0x04 // Set serializer pre-emphasis for high speed PCB
0x0066 0x03 // Foreground calibration mode with timing optimization enabled
0x002B 0x13 // Change reserved register to proper setting
0x0208 0x07 // Change over-range processing to longest interval
0x0051 0x84 // Calibration optimized for large signals
0x0201 0x0E // Scrambler off, KM1 = 3, DDR, JESD disabled
0x0200 0x30 // bypass mode, 2's complement
0x0202 0x40 // P54 PLL off, Differential SYNC, Normal data mode
0x0201 0x8F // Scrambler off, KM1 = 3, DDR, JESD enabled
0x0050 0x0E // Initiate a foreground calibration

Why the rxbyteisaligned_out signals are low? Maybe I miss something in the config?

Thanks in advance.

Dmitri.