TSW14J56EVM: External pattern file format; Multiple channels

Hi Justin,

Please see attached for the format of a 4 channel pattern file sent through HSDC Pro /TSW14J56EVM. I believe that what you are asking is achievable, but this may require two files. I will research this some more.

DAC38J84 Test_368.64MSPS_100MHzSignal.csv.zip

How are you confirming communications with the DACs and TSW14J56EVM? Have you successfully sent a pattern to any of the DAC channels? What LMFS settings are you using?

Here is a TI reference design that was done using two DAC3XJ8X and two TSW14J56EVM s. It's not exactly the same as what you have described, but it may be helpful for your design.

http://www.ti.com/tool/TIDA-00996/

Best Regards,

Dan

Thanks, Dan.

I've seen the *.tsw test files available (and have sent them to my DACs), my question was more to what those numbers represent for complex data. Would it be "Real, Imag" four times for the four channels, for a total of 8 columns?

I've successfully sent frequencies from the HSDC GUI to each of the 8 channels and verified the frequency with an analyzer. I BELIEVE I've sent one of the *.tsw test files, as well... and a *.csv, as well.

I'm using an LMFS setting of 4421, which actually brings me to another question... how to communicate with all 8 channels using one INI file? Thus far, I've used an INI file for lane 0-3 and a second file for lane 4-7 using the following lines in the ini:
"Lane Mapping=lane0:0,lane1:1,lane2:2,lane3:3"
or
"Lane Mapping=lane0:4,lane1:5,lane2:6,lane3:7"

What variables would I need to change in the INI to address all 8 lanes?

Thanks for the ref design. We'll be linking 6 of these modules together and time alignment is one of the issues on the table. It'll help a ton.

Hi Justin,

I believe that this can be accomplished, but I have not personally seen this in action. I think an issue that may arise (at least with using the TSW14J56EVM) is that both of the DACs will need to be synchronized simultaneously by the FPGA (using the SYNC signal).

As far as the ini file goes, I think you are on the right track, but I am unable to confirm. I believe you will need to use an ini file that utilizes 8 lanes (doubling most of your current ini file setting in order to support all lanes).

Best Regards,

Dan

Hi Dan,

I have the Sync lines for each DAC connected to the FPGA - the second connection was made to LA_33_P/N_A (pin G36/37 on the FMC) so that either IC can request a sync.  I'll be modifying the TSW source to utilize some additional control lines and that's one of the changes on my list.  I'd like to connect the second Sync line to TX_ALT_SYNC_P/N, but I don't think I can get the lines out without tearing up my comm lines.  There will likely be some timing differences, as the pins are on different banks, but I'm hoping I can compensate for that within the FPGA.  If you think that will be problematic, please let me know and I can try a bit harder to gain access to the ALT_SYNC pins - I found some clock issues on Friday and am in the process of moving some lines around.

For the INI file, are there any guidelines to the variables and what they mean?  I didn't want to just start changing things and end up breaking it, but I would like to have a better understanding of which variables need to be changed to utilize the full 8 channels.  If I have to use two files to load the waveforms, that would be doable, but changing INI files wouldn't be feasible.

Thanks for your help

Justin