ADS4245-EP: ADS4245-EP clkout is not proper

All three boards were working, including ADC with complete application code.  
Input clock is probed at R215 using single ended probe.
ADC CLKOUT is probed at Via near to ADC on top layer of PCB.
ADC CLKOUT is connected to single LVDS receiver in FPGA, Internal termination of 100E is Enabled inside FPGA.

Images in sequence are :

1) Board 1 - CLKin (single ended)

2) Board 1 - ADC CLKOUTp (Reduced amplitude)

3) Board 1 - ADC CLKOUTn (Reduced amplitude)

4) Board 2 - CLKin_p (single ended)

5) Board 2 - ADC CLKOUTp (Present -  approx 1Vpp)

6) Board 2 - ADC CLKOUTn (NOT Present )

7) Board showing probing locations

8) Last two images  - Schematic

In the attached images input clock is approx 1Vpp for Single ended....

Also, with the same input clock the board was working from 3 Months.

Well I will go through the ADS4245-EP input clock requirement....

The clock source what we used is L0M0KM6010E32IA, 100MHz, LVPECL .

The VCM is connected to output of AC coupled filter output to provide VCM raised inputs to ADC.

Schematic is below.

Kindly comment.

With this inputs can we confirm that ADC is not functioning, as CLKOUT is not proper.

Shall I go for replacing the ADC chip.

Any other point to check which may confirm that ADC is not functioning properly.

Kindly comment.

I will capture and post the same today...

HI,

I replaced the ADC in one of the board. Whereas after replacing ADC the situation is same. ADC_CLKOUTp is ok and ADC_CLKOUTn is with reduced amplitude.

I have captured waveforms of Input clock at R221, R222 and at R215. These waveforms looks OK. Kindly Check.

Regards,

I will Check and update you....

Related to LVPECL clock following are the details from datasheets:

1) LMK61E2-100M Datasheet: LVPCEL clock

    VOD Output Voltage Swing  = 700(min) 800(typ) 1200(Max) mV

    VOUT_DIFF_Vpp Differential Output Peak-to-Peak =  2x|VOD|

    From this Vdiff can be 2.4Vpp

2) ADS4245-EP

  CLKP, CLKM Input applied to the terminal: Max AVDD(1.8V)+0.3V = 2.1V

As you wrote the ADC plots are wrt 1.5V differential clock and ADCCLK in of 2.3585Vpp and 2.7839Vpp is not suitable for 1.8V device.

For this Pls Check Input clk probed with differentail probe which was showing Vpp of 1.8442V

In order to reduce the swing for input clock, the input 150E termination is replaced by 174E which is giving Vpp of 1.6532Vpp.

With this change the is no improvement found in the clk out of ADC.

Still CLKp is present with 100MHz and CLkn is absent.

Other Input and output clocks probed are attached for your reference.

Kindly comment on this.

HI,

I totally agree with your comments for "“CLKP, CLKM Input applied to the terminal: Max AVDD(1.8V)+0.3V = 2.1V".

I need to check the power up sequence to confirm whether ADC clock is present before ADC power up. I will do it.

Mean while for LMK61E2-100M 3.3V and ADC 1.8V device, can you pls tell me what type of termination and value is suitable for clock input instead of 150E.

Also I need to know new clock source part number suitable for ADC, for next version of schematic.

Regarding waveform plots...Plot 3 is captured with Differential probe (and I felt it is correct)... I don’t have better clarification for this, pls let me know how to capture

proper single ended and differential waveform for the clock.

One more logical doubt is that "Even though LMK is powered with 3.3V and it supports LVPECL clock output, then the clock swing should be as per standard LVPECL signal levels irrespective of the Power of the device". Kindly comment on this.

Regards,

HI,

as you wrote in last post, I check the power sequence for clock and the ADC. The ADC power 1.8V is almost 7 ms earlier compared to clock to be present for ADC.

Pls check the Plot below.

As you said I will confirm the probe impedance for both.

I will upload the Plots with 100E termination on clk.

Regarding boards,

Even the third board which was working, now have same status.

The details are :

Board 1 and Board 2 - ADC output clk   - CLKOUTp is present "100MHz", CLKOUTn - "Not present"

                                        Even then some how (may be as I am using differential LVDS receiver buffer inside FPGA), I am getting clk inside FPGA. because of which a function test is passing at present.

                                        But Note that still CLKOUTn is not present on Board 1 and Board 2.

Board 3:         Both ADC CLK p & n are continuously changing. they are not stable at 100 MHz.

Kindly comment.

The power sequence looks OK.  I still recommend to attempt to target a nominal input clock swing of 1.5Vpp-diff to match the ADC datasheet nominal value.  

At this point, I suspect the termination or configuration in the FPGA might not be correct.   I recommend removing the FPGA load from the CLKOUT (open this path) and terminate (100ohms-diff) near the ADC and probe here to determine if ADC CLKOUT is functioning properly.

Thanks

Christian

HI,

As you suspect on FPGA termination, I also suspected on this and following things I tried to check this...

1) Removed FPGA On chip termination of 100E and provided it on PCB near to ADC physically.

   -  NO improvement found in CLK outputs

2) (Then I thought may be clk site in FPGA has gone bad) Thus wired same clock outs to some other differential clock site (pins) in FPGA  and disabled the old site connection (Physically track was present. In order to isolate completely from old clk site I have to cut the track and I dont want to do it now..).

 -  NO improvement found in CLK outputs

Regards,