Dear Experts,
One of my customers is designing with our ADS4245 ADC using the LVDS interface and at 122.88MHz speed. They have some questions however about its interface due to some discrepancies in the datasheet as below:
"In the device datasheet, there is a discrepancy between Figure-6 and Figure-7 such that in Figure-6, it says the ODD bit is sampled on the rising edge of the CLKOUT signal while in Figure-7, it shows completely the opposite. Our lab tests show that Figure-6 is correct, is this true?
Also, in the same mentioned figures of the datasheet, it specifies that the rising and falling edges of the CLKOUT signal as right in the middle of the Data signal, when we analyze either of the CLKOUTP and Data pinswith an oscilloscope, we get the attached waveforms. We think that there may be a serious issue in some cases when the Data signal is also rising while the CLKOUT signal is rising. Can anyone comment on that?"
I's appreciate if anyone can comment on these issues.
Thanks,
Murat Ilhan.
Analog FAE.
