Hi,
In our design ADC12D1800 part is interfaced with Xilinx Virtex-7 FPGA.
ADC is configured for DES mode operation in Demux mode interface.
I, Id, Q & Qd signals of ADC are connected to IBUFDS primitives followed by IDDR primitives in FPGA. ADC sampling clock is 1.35Ghz. When tried to capture test pattern few samples are randomly getting corrupted.
Then tried with reducing ADC sampling frequency to 400MHz and changing Data-to-DCLK phase relationship between 0 and 90. Still test pattern is getting corrupted.
Please suggest how to capture ADC test pattern properly.
