ADS8598H: ADS8598H Readout frequency (serial and parallel)

Niels,


Unfortunately, your question requires a bit more information than I have for a good answer. A lot of the applications people are out, so it may take extra time this holiday season to get you a good answer.

I'll forward on this question, but again it may take a few extra days.


Joseph Wu

Niels,


I made a quick search and did come up with this post about the limitations of serial data read.

e2e.ti.com/.../2418341

It looks like the serial data read isn't capable of a 500kSPS readout. Let me know if that answers your basic question.


Joseph Wu

Hello Joseph,

first of all, I would like to wish you a happy new year.

for me, there is still a contradiction in the ADS8598H data sheet:

According to the technical data, it is not possible to achieve 500ksps with serial readout, even when using both data lines. But accoring to the text in section 7.4.2.3.3 "Serial Data Read", the maximum throughput (500kSps) can be achieved even with "one lane serial data readout" when using "read during conversion".

To keep it simple, you could reduce it to the following questions:

1. Is the minimum SCLK time period of 50ns from the data sheet correct?
2. Is it correct that the max. SCLK frequency is lower than the max. parallel readout frequency?
3. What is the maximum achievable sample rate when using serial readout with both data lines?

I am looking forward to your answers.
Regards, Niels

Niels,


Thank you. Happy new year to you too.

Let me start with the questions directly:

1. I believe it is correct that the minimum SCLK period is 50ns. The timing information in the datasheet is usually based simulation and then characterization of the process used for the design.

2. I'm not sure I understand this question. Are you asking if max SCLK frequency should be faster to get out the 500kSPS data rate that can be clocked out using the parallel readout method?

3. I believe that the max sample rate with serial readout is 278kSPS. I still think that it is not possible to achieve 500kSPS with serial readout and this is stated incorrectly in the datasheet. This is was was commented on in the post that I provided a link to.

I will admit that I'm not the normal support for this product (I was filling in during the holiday break). I'll check in with the normal support and see if he has any alternate answers or comments.


Joseph Wu

Joseph,

even though you are only the vacation replacment, your answers are more helpful than some of the expert answers I got in the past.
Thank you for your help so far.

Let me give you some explanaition to question 2:
My experience with other devices is, that serial interfaces can typically clocked faster than parallel interfaces.
With the ADS8598H, it seems to be the other way round:
For serial readout, the minimum SCLK time period is 50ns, which leads to a max. serial readout frequency of 20MHz.
For parallel readout, it is the RD# signal that times the length of the data access, thus acting as a kind of clock signal. The minimum RD# low and high times are 15ns both, summing in 30ns for one "clock" cycle. This leads to a max. parallel readout frequency of 33.33MHz.
As you can see, the ADS8598H can output its data at a rate of 33.33MHz when using its parallel interface. But when using the serial interface, the rate is reduced to 20MHz.

Until now, nearly a whole year passed by since the first question to this topic came up: click here
But the ADS8598H data sheet is still unchanged. I wonder why.

It would be nice if someone from the expert group could give his comments to my questions after they returned from their vacation.

Regards, Niels

Hello Joseph,
206kSps is not the answer I hope for. But anyway, thank you for your help.
I will use the button you suggested.

Regards, Niels