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Original question:

TLV5614: LDAC* Pin's Timing Requirements/Specs are not on the Datasheet

TLV5614: TLV5614 power on sequence

Jeff Xie
Intellectual 1780 points
Part Number: TLV5614

Hello team,

TLV5614 is used on a mass production project. About 1% of TLV5614 will have a problem that before MCU configure TLV5614 via SPI bus, the analog output OUTA~OUTD of TLV5614 will output 5V voltage (analog power supply of chip is 5V), which leads to abnormal operation of the machine.

The TLV5614 of the normal working machine analog output OUTA~OUTD output is 0V voltage before configuration. Replacing faulty chips to good machines can cause the same problem.

Further research found that the chip's AVDD power is power on 4 ms earlier than the DVDD, and the failure disappeared when the power on sequence was modified to DVDD first.Referring to the specifications of TLV5614, no description of the timing of power-up was found.

Does TLV5614 have clear requirements for power-on timing? Is the TLV5614 chip that output abnormal damaged? 

Thanks

  • 0
    TI__Genius 14220 points
    Hi Jeff,

    Thank you for your query. The failure could be because of the power supplies as you have pointed out. There is no explicit power supply sequencing requirement for this device as such. However, the ABS max table specifies that the difference between AVDD and DVDD should be less than +/-2.8V. When there is a gap between these two supplies of 4ms, there is a possibility that this limit was violated. This might have damages the devices.

    Please also look at the reference voltages. They should not be on before AVDD as per the ABS max table. This could be another suspect that might result in device damage.

    Hope that helps debug the issue. Please let us know if there is any new finding.

    Regards,
    Uttam Sahu
    Applications Engineer, Precision DACs