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ADS1282: ADS1282

Part Number: ADS1282

E2E;

I am reviewing the 4th order Modulator to assure I understand it correctly. In the world of SAR ADC a data point is represented by a digital word associated with Vin. A delta sigma creates a PCM a frequency representation of the data point. My question is how long does it take to create this PCM? My overall goal is to determine the total time it takes to sample a data point and download the data into a FPGA. Looking at Figure 35 Modulator Mode Timing (Page 17 of ADS1282 Datasheet) I assume it will take approximately 16us to run through Equation 5 (page 15 of ADS Datasheet.) and fully download the 32bits via 2 pins to the FPGA.

With fmod = (fclk/4) = 1Mhz = 1us

16bits * 1uS = 16uS

Thanks

Dean Gacita

  • Hi Dean!

    I'm curious, how did you make out with the EEPROM? I see now where the 16uS comment came from in one of the previous posts as well. I believe Chris mentioned to you that the data you pull out of the modulator is not going to be true 32-bit conversion data, it's going to be a multi-bit bitstream that you would need to filter in your FPGA. In the standard operating mode of the ADS1282, the modulator data is a continuous stream of 1's and 0's being sent to either the FIR or SYNC mode filter. The decimation ratio set by the data rate register controls the rate at which the final conversion result (the 32-bit word you seek) is made available in a buffer to be sent through the SPI interface.

    In modulator mode (filter bypass mode), you need to perform the digital filtering yourself - i.e. create your own SYNC or FIR filter with your desired oversampling rate so that you can tune in the data rate of your choice.
  • Tom;

    On the EEPROM front our setting was set to false. To prove to ourselves that this works we changed the address to the EEPROM to a different value on TIs eval board. Assuming that if the EEPROM verify was set to false it would not mattered what the address was set to. However the system failed to boot. Our thought was the system must be writing something to this EEPROM to verify it functionality not just to read some predetermined data previously placed in the EEPROM at manufacturing. Our board we are going to interface with the BurrBrown board has the same EEPROM on board with the same address. Hoping that is all we need to do.

    Yes Chris had responded to my 16uS question. However, still a little fuzzy so thought I would address it again. Both you and Chris are moving me along. I now believe that the 16uS does not mean anything. What I am looking to confirm is that the data out of the Modulator is coming at me at MCLK which is at 1us two bits at a time. If I was to use the on chip DSP (Filtering) and based on the SPS I will get very accurate data at SPS/2 bandwith.

    Let me know if I have the concept of MCLK correct. Thanks
    Dean
  • Hi Dean,

    I can address the point regarding the 16 us...

    You are correct that data comes out at a rate of MCLK (fCLK/4)...

    However in a previous discussion, I believe you were asking about how much time it takes to get data out of the ADS1282 in modulator mode. Coming back to this topic, if you refer to table 4 there is a 16 us timing specification from SYNC to stable modulator output data. So yes, you'll read the data at a rate of ~1 MHz (MCLK), but you'll want to disregard the first 16 samples after starting a new conversion.

     

  • Chris;

    Yes you are correct on the original 16us question. In studying this device I may ask repetitive questions to continue developing my understanding of Delta-Sigma ADCs.

    The reason I am concerned with MCLK is I want to provide a feature in our design where continuous data is being provided to the controller. The command (Read Data Continuous) is of interest to me. How will Mode data coming out of the modulator look like? Figure 56 represents the SPI output so looking for what the Mode data looks like.

    After the controller initializes a SYNC and the command is to read continuously - will there be any interruptions in the MODE data stream? I realize the controller will have to process the data through a digital filter within the controller. It maybe better if the controller initializes a SYNC each time but I do not want to wait the 16us for new valid data.

    Thanks
    Dean Gacita
  • Hi Dean,

    Not a problem, I hope that clarified at least where the 16us timing requirement was coming from.

    In modulator mode you will have two PWM signals (bitstreams) that you will have to sample. After acquiring these bit streams and performing the math function given by equation 5, you will have a 1-bit conversion result.

    The ADS1282 datasheet does not have a figure showing the modulator output data (Figure 56 shows SPI data after it has be processed by the ADS1282's digital filter). The best figure/explanation I can point to for modulator mode is this blog post: e2e.ti.com/.../delta-sigma-adc-basics-understanding-the-delta-sigma-modulator

    In modulator mode, the RDATA, RDATAC, and SDATAC commands shouldn't have any effect on how the ADS1282 outputs the modulator data, so I don't seen any purpose for using them.

    After a SYNC command, I don't think you will see any interruptions in the modulator data, but it would be best practice to ignore the next 16 modulator samples. After talking to a digital designer, I was informed that the M0 data may not actually need to be ignored, but rather the M1 data (the 2nd stage modulator data) is more probably not settled, so the next 16 samples (if included) would include much more noise in the bitstream.

  • CORRECTION: RDATA, RDATAC, and SDATAC, should NOT have any effect on the modulator output data.
  • Chris;

    Thanks - Is it possible to have a 10-15 minute conversion on the phone. I need to understand Eq5.

    Thanks
    Dean
  • Hi Dean,

    I'm happy to have a chat with you, and if need be, we can bring in Chris as well. If it's OK with you, I'll send a note to your TI.me e-mail address to try and setup a convenient time.
  • Hi Dean,

    I give an example of this calculation with dummy data in a previous post: e2e.ti.com/.../2789777

    Please give that a look to see if it helps...
  • Chris,

    Y[4] = 3M0[4-2] - 6M0[4-3] + 4M0[4-4] + 9M1[4] - 2M1[4-1] + M1[4-2]
    = 3M0[2] - 6M0[1] + 4M0[0] + 9M1[4] - 2M1[3] + M1[2]
    = 3[0] - 6[1] + 4[0] + 9[0] - 2[1] + [0]

    if 0 (GRN) is positive weight
    & 1 (RED) is Negative weight

    = 3[1] - 6[-1] + 4[1] + 9[1] - 2[-1] + [1]
    = 3 + 6 + 4 + 9 + 2 + 1
    = 25

    Y[15] = 3M0[15-2] - 6M0[15-3] + 4M0[15-4] + 9M1[15] - 2M1[15-1] + M1[15-2]
    = 3M0[13] - 6M0[12] + 4M0[11] + 9M1[15] - 2M1[14] + M1[13]
    = 3[1] - 6[0] + 4[1] + 9[1] - 2[0] + [1]

    Now
    if 1 (GRN) is positive weight
    & 0 (RED) is Negative weight

    = 3[1] - 6[-1] + 4[-1] + 9[1] - 2[-1] + [-1]
    = 3 + 6 - 4 + 9 + 2 -1
    = 15



    I am unable to get your numbers in the example. I also do not understand the change in weight bit.

    Thanks
    Dean Gacita
  • Hi Dean,

    It quite possible I may have made a mistake, but I think you might be confusing "3M0[n-2]" for "3*(4-2)" when this should be "3*0".

    "M0[n-2]" represents the value of M0 two samples earlier.

    Here is the Excel File for your reference: /cfs-file/__key/communityserver-discussions-components-files/73/ADS1282-Bitstream.xlsx

  • Chris,

    I see my mistake Thanks for the spreadsheet - Now to round things out I understand Y is a multi-bit, bitstream. How wide is Y? ie 8 bits wide I assume it is a parallel bus.

    Thanks
    Dean
  • Hi Dean,

    No problem. I went through the exercise of creating that spreadsheet partly for myself to realize that "Y" is a multi-bit stream. "-24" and "25" were the limits I calculated so you need at least 5-bits to represent "Y".