We cannot get our DAC38RF82 SERDES PLL to lock (We tried and failed on four different PCB assemblies).
We checked all supply voltages, grounds, and input signals and they seem OK. We can write and read the control registers over SPI. We do not believe it is an assembly issue or board design issue.
The DAC PLL locks and we configured it to accept a ~122MHz differential input clock on pins DACCLK+/- with an output of ~5.898GHz. This was verified by measuring a ~5.898GHZ divided by 4 clock on the CLKTXP/N differential output pins.
We set the SERDES_REF_CLK_DIV to divide the DAC PLL ~5.898GHz output by 12 to produce a ~491MHz input clock to the SERDES PLL. We set the MPY bits to multiply the 491MHz input clock x5 to produce an output of ~2.45GHz. The ALM_SD0_PLL flag is set indicating an unlocked SERDES PLL (register 0x05, bit 2). To verify, we set ENDIVCLK to produce a SERDES PLL output divided by 80 on the ALARM pin. We do not see a clock on the ALARM pin (it's 0V).
Our configuration register values are shown below.
Can you help us debug this issue?
Thank you.
Best,
Scott
{0x31, 0x0400}, // DACCLK (diff) selected (122.88MHz), PLL_ENA=1, PLL_N_M1=0+1, LOCKDET_ADJ=x00.
{0x32, 0x0B0F}, // PLL_M_M1=(11+1), PLL_VCO_RDAC=15. // PLL = 122.88*4*12 = 5898.24MHz.
{0x33, 0x383C}, // PLL_VCOSEL=0 (lo), PLL_VCO=(?), PLL_CP_ADJ=15.
{0x34, 0x0000}, // LVDS_CONFIG default, SYNC0 powered up.
{0x35, 0x0018}, // PLL_FDIV=24 for Fuse Farm.
{0x3B, 0xD800}, // SERDES_CLK_SEL=PLL_out, SERDES_REFCLK_DIV=(11+1), SERDES_REFCLK_PREDIV=Div1.
{0x3C, 0x9029}, // EnDivClk=1 (TP=SerDesPLL/80), CLKBYP=00 (?), LB=low=10, SLEEPPLL=0, VRANGE=0 (SERDES PLL 2457.6>2170MHz), MPY=5x (00010100!), Correct=1.
{0x3D, 0x0088}, // ENOC=1(SERDES offset comp), EQHLD=0, EQ=001 (No boost, fully adaptive eq), CDR=000.
