Compiler/ADS1299: ADS1299

Hello,

thank you for the reply.

I wrote the following code for mbed compiler and it is quite understandable. 

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#include "mbed.h"
#define F 1000000 // 1 MHz

SPI spi(PA_7, PA_6, PA_5); // mosi, miso, sclk
DigitalOut cs(D4);

int main() {

long int data_in;

// Setup the spi for 8 bit data, CPOL = 0, CPHA = 1 (mode 1) , with a 1MHz clock rate
spi.format(8,1);
spi.frequency(F); // SCLK_F = 1MHz

cs = 1;
wait_us(10);
cs = 0;
spi.write(0x06); // reset
cs = 1;
wait_us(10);

while(1)
{
cs = 0;
spi.write(0x11); // send SDATAC
spi.write(0x25); // select channel 1
spi.write(0x00);
data_in = spi.write(0x00);
printf("data in = %d\n", data_in);

spi.write(0x10); // send RDATAC
cs = 1;
wait_us(10);
}
}

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As output i get only zeros.

Do I need to initialize any other signals such as DRDY and START?

Is the communication flow correct?

I'm powering the ADS board through MMB0 board without using the ADS software.

Do I have to power it in some other ways?

I post a picture below to show the HW setup.

Hello,
I'm trying to interface the ADS1299eeg through SPI but I'm facing with a lot of problems. Actually I menaged to read various internal registers but the problem occurs 
when I try to read the digital values of the analog inputs after conversion. In particular I can't obtain a correct behaviour as far the DRDY signal is concerned: the output is not as expected,
 consequently it looks that data are never ready and the read value after START is always the same.

I'm following the flow explained in chapter 10.1.2 of the datasheet but I'm wondering if I have to follow a different procedure since I'm powering the ADS board through the MMO motherboard.
 In fact, as soon as I power it I verified that PWDN, RESET and START pins are already 'high' as the flow indicates. 

Could you make a summary of the right procedure and commands that I need to send in order to get a correct DRDY behaviour and to obtain the data in general? 

In case I want to power the ADS board in a different way, which is the best way to make the interconnections?

The above picture the blue line refers to SCLK and yellow DOUT, the DRDY  is always high isn't toggling.