ADS54J66: JESD word format structure.

sai kiran56

Part Number: ADS54J66

Hi,

I'am using ADS54J66 evaluation board for JESD interface bring up. the ADC which is used inside the evaluation board is ADS54J66.

This ADC is a 14 bit ADC but as per JESD format they are formatted to 16 bit data by adding control bits or tail bits.But for the above mentioned ADC i'am not able found how the ADC will format the 14 bit ADC sample data into 16 bit JESD word format by seeing ADS54J66 ADC datasheet. can anyone explain.

Thanks in advance.

over 6 years ago

0 jim s over 6 years ago

TI__Guru* 91947 points

Sai,

There are 2 tail bits added to the end of the 14 bit word. The LSB can also be used as in over range bit if set in the appropriate register.

Regards,

Jim

0 sai kiran56 over 6 years ago in reply to jim s

Prodigy 120 points

Hi jim,

1. Is adding tail bits means padding zeros at the end of the sample?
2. The MSB eight bits of the sampled ADC data is not effected (that is padding of control or tails bit will not take place at that position) ?

Thanks for quick reply

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ADS54J66: JESD word format structure.