• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 871 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADS7953: Capacitance at REFP and REFM pins

ADS7953: Overall sampling rate and effective sampling rate

Andreas Nestler
Intellectual 350 points
Part Number: ADS7953

How can I calculate the overall and effective sample rate, which is achievable with the ADS7953? According data sheet the max SPI clock frequency is 20MHz and the device needs 16 clock cycles for conversion (table in chapter 7.9). According this I would assume a max. throughput of 1.25MS/s. However in datasheet a max. sample rate of 1MHz is specified. How can I derive this value? Simply it woiuld mean that we need a total of 20 clock cycles per conversion but this is not mentioned at all within the datasheet. Furthermore we need to sample each channel, so the effective sampling rate (per channel) is 1/16th of the overall sample rate because the ADS7953 has 16 channels total. Is this calculation correct or do I miss something? Back to an example: SPI clock 20MHz -> overall sample rate 1MS/s and effective sample rate per channel would be 62.5kS/s. Could sou confirm this calculation?

Best Regards Andreas

  • 0
    TI__Mastermind 24970 points

    Hello,

    Your calculations are done correctly. What is different about this device though is that the acquisition and conversation time, when added, do not add up to the throughput rate. I will point out that this is not the usual case, in most devices, they do add up.

    The conversion time of this device is actually 800ns, with the acquisition time of 325ns. when added this does not give the 1uS expected for the 1MHz throughput rate. That is because, from the timing diagram below, the two actually overlap. If now then, you take the 800nS of conversion time, it works out.  SCLK= 20Mhz = 50nS, then multiply that by 16, results in 800nS.

    Regards

    Cynthia

  • 0 in reply to Cynthia
    Intellectual 350 points

    Dear Cynthia,

    many thanks for the explanation. Still I have some issues with the aquisition time. In datasheet there is a minimum time of 325ns specified.  If this is the minimum time, what could be the maximum? As far as I can see from datasheet the user has no impact to the aquisition time. Does it mean if I reduce the SPI clock speed from 20MHz to 10MHz is then the aquisition time the same so independent from SPI clock or twice the value with SPI clock of 20MHz meaning aquisition time depends from SPI clock?

    Regards Andreas

  • 0 in reply to Andreas Nestler
    Intellectual 350 points

    In addition to my question above. I cannot understand the timing parameters after the 16th clock cycle. Taken the 20MHz SPI clock as an example (Tper=50ns) the aquisition phase requires at least 325ns as you have also highlighted in your response. The aquisition phase starts at the fourteenth (14th) clock cycle so altogether 3 clock cycles (150ns) which leads to the requirement that the following falling edge of CS has to occur earliest 175ns after the end of the 16th clock cycle, which equates to 3.5 clock cycles (each 50ns). According the timing diagram values there is time tq to consider, which is much less than the required 175ns.

    So if we like to realize the interface to the ADC via programmable logic we have to know the correct timing constraints and it is a bit difficult to find out of the datasheet. So the basic question is regarding the rising and falling edge of CS after the 16th clock cycle.

    Regards Andreas

  • 0 in reply to Andreas Nestler
    TI__Mastermind 24970 points
    Hello,
    Apologies for the late response.
    The acquisition time can be as long as you would like, as long as it is longer than the minimum time of 325ns. It is not fixed.
    The device stays in acquisition phase starting from 14th rising edge, until the device received a falling edge on CS. This is completely up to the user.
    I can see the confusion. When looking at the CS, the maximum through put is 1MSPS, which equates to 1us. Have the falling edge of CS at a period no less than 1us.

    Regards
    Cynthia