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DAC38RF82EVM: 12b Single Mode CMODE 5 LMF=413 Setup

Part Number: DAC38RF82EVM


I am able to test clock modes other than 12b single CMODE5 successfully with the DAC38RF82EVM.  The end use case for our project is single DAC, 2.66GSPS 12b, 1x interpolation, 4 lane.  I have connected my clocks per the CMODE5 setup instructions - two signal generators with a common reference one to J4 and one to J1.  I have tried setting the J4 reference to 1/4 of Fs (J1) and also to the frequency recommended by the HSDC GUI when the config is LMF=413.  Neither setup shows an output to the spec-an.  What other settings do I need to hit and what frequencies do I need to set my generators to?  The manual is not clear.

  • Hi Chris,

    Note the serdes rate (Fserdes) reported by the GUI and set the clock frequency at SMA J4 to 1/20 x Fserdes. This clock will be divided down further by 2 to provide 1/40xFserdes as reference clock the FPGA.
    Also, as a quick test, enable the mixer and constant data to the NCOs and set NCO frequency to 1GHz and check for a tone at 1GHz. This will confirm the clocks are set up correctly.

    Thanks,
    Eben.
  • Hi Eben,

    I have set the J4 clock to 500 MHz (10000 MHz/20) @+6 dBm as indicated by the GUI and your response. The 2.666666 GHz J1 sample clk is +16 dBm per the manual.  Other than quick start no software changes were made.  I've attached images of both the EVM GUI and the HSDC software GUI. JP10 is open.  I had no luck generating the 700 MHz tone indicated on the HSDC software.

    I attempted the test you mentioned enabling the mixer and NCOs and could not get any output.

    Is there something else I need to change in the setup?

    Thanks

    Chris

  • Hi Chris,

    Enable constant data as shown below: If you can confirm you have an output, then we can be sure your setup is right.

    Also, check on TSW14J56 that LED D1, D7 and D6 are off and D2 is blinking.

    Thanks,

    Eben.

  • Eben,

    By enabling the "constant" input I was able to get the output to change.  See below.  First image is with constant input and the second is without (spur is just fs) which is what I see when trying to generate a signal using HSDC or just doing nothing.

    Chris

  • Hi Chris,

    Contact me privately so I can schedule a conference call with you to troubleshoot this further. I will like to walk through the bring up with you

    Thanks,

    Eben.