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Original question:

TINA/Spice/DAC8822: DAC8822

DAC8822: DAC8822QCDBTR

cp umashankar
Prodigy 150 points
Part Number: DAC8822
Other Parts Discussed in Thread: OPA277

Hi Technical Support,

We have simulated using TINA DAC8822 and got the required simulation output without any issues.

But when we launch the product using the simulated Schematics we have not getting the output as per our TINA simulation.

My Application calls for update data rate of 1us ( total of 80 data the total duration is 80 x 1us = 80us). 

So we are using Clock of 1MHz = 1us update rate i.e 1us.

Please find the attached document of output of TINA, Schematics of DAC on product and our observation in the document.

If we put the data @ 1MHz rate = Distorted wave.

if we put the same data @ 250KHz = Required out is achieved. at around 320us. But our application calls for 80us.

Kindly revert back , since we are at the critical end of the product launch.

DAC-8822.docx

With  Regards

C P

  • 0
    TI__Genius 14220 points
    Hi Umashankar,

    Thank you for your query. Could you please upload your TINA file? The image attached in the doc is not clear enough.

    Regards,
    Uttam
  • 0 in reply to Uttam Sahu
    Prodigy 150 points

    Hi Uttam Sahu,

    Please find the attached file.

    With Regards,

    C P

    Macro code used.

    =================

    ------------------------------------
-- TINA HDL Macro Description Begin
-- 
-- entity_name:simplified_wave;
-- arch_name:ignored;
-- ports:Clk,Reset,Enable,Sel0,Sel1;D15,D14,D13,D12,D11,D10,D9,D8,D7,D6,D5,D4,D3,D2,D1,D0,Write;
-- Mode:VHDLTyp;
-- 
-- TINA HDL Macro Description End
------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

entity simplified_wave is
  port ( Clk : in std_logic;
       	 Reset : in std_logic;
         Enable : in std_logic;
         Sel0, Sel1 : in std_logic; -- 0: sine, 1: saw, 2: square wave
         D15 : out std_logic;
         D14 : out std_logic;
         D13 : out std_logic;
         D12 : out std_logic;
         D11 : out std_logic;
         D10 : out std_logic;
         D9 : out std_logic;
         D8 : out std_logic;
         D7 : out std_logic;
         D6 : out std_logic;
         D5 : out std_logic;
         D4 : out std_logic;
         D3 : out std_logic;
         D2 : out std_logic;
         D1 : out std_logic;
         D0 : out std_logic;
	 Write : out std_logic
         );
end simplified_wave;


architecture simplified_wave_a of simplified_wave is
  -- ROM declaration
  constant LUT_index_min: integer := 0;
  constant LUT_index_max: integer := 80;
  type ep_LUT_typ is array (0 to 80) of std_logic_vector(15 downto 0);
  constant ep_LUT : ep_LUT_typ :=("0000111111000110","0000111111000110","0000111111000110","0000111111000110","0000111111000110","0010001000101110","0010001000101110","0010001000101110","0010001000101110","0010001000101110","0010001000101110","0000010110001111","0000010110001111","0000010110001111","0000010111110110","0000010111110110","0011111111111111","0011111111111111","0011111111111111","0100000000010000","0100000000010000","0010001110111101","0010001110111101","0010001110111101","0010001110111101","0010001111110000","0010001111110000","0010001111110000","0000001010101011","0000001010101011","0000001010101011","0000001010101011","0000001010111100","0000001010111100","0000001010111100","0001111110001001","0001111110001001","0001111110001001","0001111110100100","0001111110100100","0011111010111000","0011111010111000","0011111010111000","0011111010111000","0011111010111000","0010000110111011","0010000110111011","0010000110111011","0010000110111011","0010000110111011","0010000101011101","0010000101011101","0010000101011101","0010000101011101","0000000000110111","0000000000110111","0000000000110111","0000000000110111","0000000000110111","0000000000110111","0000000000110111","0000000001101011","0000000001101011","0000000001101011","0000000001101011","0000000001101011","0011111101100111","0011111101100111","0011111110101100","0011111110101100","0011111110101100","0011111110101100","0010001011011110","0010001011011110","0010001011011110","0010001100101000","0010001100101000","0010001100101000","0000111111011110","0000111111011110");
  signal LUT_index : integer range 0 to 80;
  signal Wave : std_logic_vector(15 downto 0);
  
begin

 process(Reset, Clk, LUT_index, ep_LUT)
 begin
  if (Reset = '1') then
   Wave <= (others => '0');
   LUT_index <= 0;
  elsif rising_edge(Clk) then
   Wave <= ep_LUT(LUT_index);
   if (LUT_index = LUT_index_max) then
    LUT_index <= 0;
   else
    LUT_index <= LUT_index + 1;
   end if;
   
  else
   D0 <= Wave(0);
   D1 <= Wave(1);
   D2 <= Wave(2);
   D3 <= Wave(3);
   D4 <= Wave(4);
   D5 <= Wave(5);
   D6 <= Wave(6);
   D7 <= Wave(7);
   D8 <= Wave(8);
   D9 <= Wave(9);
   D10 <= Wave(10);
   D11 <= Wave(11);
   D12 <= Wave(12);
   D13 <= Wave(13);
   D14 <= Wave(14);
   D15 <= Wave(15);
  end if;
 end process;


end simplified_wave_a;

    ================

    Analog-Circuit-400nF-Load-8-Mosfet - autosave 19-04-10 17_50.TSC

  • 0 in reply to cp umashankar
    Prodigy 150 points

    Hi Uttam Sahu,

    Kindly update the status. Since we are in the critical stage of releasing our product.

    With Regards,

    C P U

  • 0 in reply to cp umashankar
    TI__Genius 14220 points
    Hi Umashankar,

    Apologies for the delay. I couldn't still open the TINA file. It might have got corrupted while uploading. Is it possible for you to input a single-tone sine wave with around 10-points per cycle so that we can see what might be happening?

    Regards,
    Uttam
  • 0 in reply to Uttam Sahu
    Prodigy 150 points

    Hi Uttam Sahu,

    Please find the attached output as per your suggestion.

    Find the attached document. Our problem in not in simulation. When do the same experiment on the Hardware.

    Kindly get our schematic reviewed by hardware team and give us input

    With Regards,

    C P UmashankarDAC Single tone sine wave.docx

  • 0 in reply to cp umashankar
    TI__Genius 14220 points

    Hi Umashankar,

    Apologies for the delay. It looks like the model is implementing some parameter as ideal values, which is why you are observing a degraded performance on the actual hardware. It is not possible to implement all AC parameters inside a SPICE model and expect it to converge in time as well. So, usually, they do some trade-off. I am trying to create the simulation circuit myself and analyze. 

    So, there are two possibilities: the BW gets limited by the DAC or the opamp. One way is to replace your opamps by higher BW versions and test on hardware. They are usually pin-compatible.

    I will try to get back with my simulation results by tomorrow.

    Regards,

    Uttam

  • 0 in reply to Uttam Sahu
    TI__Guru 53633 points

    Hi Umashankar,

    Have can you try disconnecting all additional circuitry after the output of the OPA277 connected to the DAC?  It seems like your are being slew-rate limited, but that rate is much lower than the OPA277 should be able to drive.  This could be an external load causing this? Is the OPA277 getting hot? Could it be short-circuit limited?  Can you verify that the compensation capacitor on that is connected to the FB node of the DAC/OPA is the correct (15pF?) value?

    Thanks,

    Paul