DAC38RF82EVM: Register settings required for the 81180 for operating at 6.4 Gsps

Hey Rajesh, 

We are looking into your question and will get back to you ASAP. 

Regards, 

Yusuf

Rajesh,

Will the DAC use an external 6.4GHz clock or use the internal PLL? What is the 200MHz reference clock you mention? Do you plan on using this with the DAC PLL?

Regards,

Jim

Hi Jim,

Since we need to operate in single channel 8 bit mode (81180) at 6.4 GSPS as max sampling rate achievable by the ADC is 6.4 Gsps.

We need to send the adc data to dac. design parameter's for DAC as follows.

Line rate set for JESD serdes lanes is 8 Gb/s. Jesd Reference clock for JESD IP core (xilinx) is at 200 MHz. Tx Core clock from the IP is also same as 200 MHz.

Currently for evaluating with the KCU105 board i need to provide 6.4 GHz Clock, if it cannot be generated through internal PLL, may be we can provide it external through signal generator and evaluate the DAC operation on first hand for the 6.4 GSPS. on the custom board we make it can be generated through the LMX259X PLL.

Can you please give the details of how to set and check for 81180 mode at 6.4 GSPS data rate.

I had discussion with your Bangalore team, they suggested to first evaluate the DAC with arria10 evaluation board to get started. 

Regards,

Rajesh

Hi,

please find the setup diagram may help you in understanding.

I need the settings for LMK04828/DAC38RF82 for below application.

6.4G_LMFS_8118.cfgRajesh,

The config file is attached. This works with our TSW14J56EVM (Aria V).

Regards,

Jim

HI,

We are trying to make the setup up with arria + dac38rf82.

Went to HSDC pro software and connect to the TSW14J56revD Board.

Selected the DAC and firmware as DAC38RF8X_LMF_811. We have set the sampling rate as 9000.

When we configure this set up we get 22.5G as lane rate but we have to get 11.25 G as lane rate.

Please confirm whether we are following the correct steps.

I have followed the steps as per the following presentation but still we are not able to get the things running. we get only a fixed 400 Mhz at the output of spectrum analyzer.

1541.DAC38RF82_real_811_8_bit_mode.pptx

Rajesh,

HSDC pro has an error when it displays the serdes rate with this mode. Just make sure the LMK clkout 0 & 1 has a divide by 8 to provide a 281.25MHz to the FPGA. Double check all of your settings and make sure they match the ones in the document.

Regards,

Jim

Hi Jim,

We spend entire day configuring various options/settings in the DAC EVM with arria. we did not manage to generate the frequency tone we want on 81180 mode.

Request you to kindly go through the attached ppt, we don't know where we are making mistake as this setup supposed to work on the mode specified.Fs_6400_81180.pptx

Rajesh,

Sorry for not getting back sooner. Please do the following changes to your procedure:

1. Change K =19 on JESD block page. This is what the FPGA will be set to.

2. Leave N and N' as 15.

3. On SYSREF and SYNC tab, change the SYSREF divider to 320.

This should give you a 200M tone at the DAC output. If you want to use the NCO, you must use I/Q data, not real data. Then on the Digital(DAC A) tab, you must enable the mixer and NCO and provide a NCO frequency. After this, click on "UPDATE NCO" to load the NCO frequency registers.

Regards,

Jim