ADS58C48: ADS58C48--100 MHz is tested help

ADC power supply:

The 1.8V of DRVDD is provided by a circuit board TPS82130

The 1.8V of AVDD is provided by NCP566M.

The ground signals GND and AGND2 between the two power sources are connected by a magnetic bead L20. L19 is not welded. L20 welding.

ADC Work Brief:
A pair of differential I/O of zynq FPGA generates a differential clock (FPGA2ADC_CLK_P and FPGA2ADC_CLK_M) to ADS58C48 through the primitive IBUFGDS. The ADC outputs a pair of clocks (CLKOUTP and CLKOUTM) as sampling clocks of the FPGA.

ADC software configuration:
The logic code of the FPGA sets 0 for reset, pdn, snrb_1 and snrb_2. The ARM code configures the register of ADC through SPI to achieve the following operations.
1) Write 0x00 register 0x02 to achieve a soft reset;
2) Write 0x45 register 0x00 to ensure normal working mode.
3) Write the TEST PATTERN register, which is the output data when entering the test mode.

3. Test problem point: VCM exception

1) According to the manual, the 29-foot Vcm of ADC should output 0.95V. After power-on, the actual measurement is 1.1V~1.6V, which is unstable.

Reading Data Problem (Test Mode)
ADC supports test mode and can output fixed data to the output data bus. In this mode, 5MHz input clock is used as ADC. The data acquisition is normal. At high speed, 100 MHz is tested, and the data acquisition is incorrect, could you tell me why?

ADC CLK：

ADS58C48_SCH.pdf