Other Parts Discussed in Thread: LMK04828, DAC38RF82
Hello.
Setup: I have a DAC38RF82EVM , and I'm attempting to use it with a Xilinx VC707 and TI's interposer board - TSW14J10.
Problem: I'm unable to see a sine wave generated by HSDCP on my scope without NCO and mixer.
On the other hand:
- I am able to output clear sine using the "Constant input" checkbox with mixer and NCO.
- I created a CSV file with a constant value, load it with "Load external pattern file" and send, with mixer and NCO enabled, I also see a clear sine.
Can someone help please?
Details:
I'm attempting to use it according to the powerpoint presentation from : 
I don't connect a 10 Mhz clock to J4, so I don't expect D3 to ever light up.
D4 remains off, even though it should go on, indicating LMK VCO1 locked.
However, the DAC's PLL does lock.
In accordance with the interposer manual, section 6, I configured the LMK to output 384 Mhz DCLKOUT0 - JESD reference clock and 192 Mhz to DCLKOUT12 - JESD CoreClock.
It seems that the FPGA is "good" - VC707 Leds 0,4 are on ( DAC SYNC indicator, DAC JESD mode enabled ), and leds 5,6,7 are blinking.
Also D8 - JESD SYNC on the EVM is on.
When I configure HSDCP to generate a 200 Mhz, I see on the scope a sinewave signal that looks good, only it's 192 Mhz, not 200.
The lower I go from 200, the more distorted 192 Mhz wave I get.
I configured DAC B to use constant input with NCO at 48 Mhz and mixer so we can easily see the signal on the scope and compare.
The following is a snapshot of me trying a 48Mhz sine on channel A, and a 48 Mhz sine generated by NCO and mixer on channel B.
The following is me trying to generate a 150 Mhz sine on DAC A, and DAC B generated 48 Mhz as above:
