Linux/DAC81416EVM: Access Register for DAC81416EVM

Daniel,

I would encourage you to look at Table 2 and Table 3 on page 28 of the datasheet. This illustrates the basic frame structure for the device with the CRC mode disabled.

Essentially each frame is 24-bits wide. The MSB, bit 23, is a read/write bit - if set to 0 it is a write operation, if set to 1 it is a read operation. Bit 22 is unused or a don't care bit. Bits 21-16 contain the register information - either the desired register to be read or the desired register to be written. In the case of a write operation bits 15-0 contain the data for the write cycle, in the case of a read these bits are not used. All of this is shown in Table 2.

Table 3 explains the structure for the read frame. It is basically the same where bits 23-16 are echo'd from the previous frame (the read request) and bits 15-0 contain the requested data.

A write to the SPICONFIG register is only a single write. This would be 0b10000011xxxxxxxxxxxxxxxx, or 0x83XXXX, where the x's are don't-cares based on your desired configuration and in this case I elected to set bit 22, the don't care bit, to zero.

Daniel,

I see that you have rejected the answer but not posted any follow up questions. Please clarify where any remaining confusion may reside.