Linux/DAC81416EVM: Clock pahse and polarity setup for SPI communication

Daniel,

As long as the timing requirements illustrated in Figure 45 and Figure 46 are met there is not a specific required clock phase and clock polarity settings. The critical edge is the falling edge of SCLK, so either CPOL = 0 and CPHA = 1 can be used or CPOL = 1 and CPHA = 0.