DAC38RF89: Looking for a process to cover transmitter pre and post cursor EQ settings using EQOVER and EQUNDER

Hi Douglas,

One of our device experts will be with you soon.

Best Regards,

Dan

Douglas,

Can you please provide more information.

1. What rate is the DAC sample clock?

2. What is the serdes rate?

3. What FPGA is driving the device?

4. Have you tried using the eyescan feature of the DAC?

5. How many lanes? How many are reporting this problem?

6. What type of board material are you using? How long are the traces?

7. Have tried any adjustments on the transmitter side?

Regards,

Jim

1. DAC Sample Clock is 7.5 GHz (input clock 2.5 GHz, input clock to FPGA 312.5 MHz)

2. SERDES rate 12.5 GHz

3. Altera

4. No JTAG access was not provided on the board.

5. 8 lanes (2 links of four lanes), we are still in the process of getting the procedure down but it looks like 3 lanes may have an issue.

6. I'll have to get back with this information (but the DACs are located close to the FPGA so traces should be relatively short).

7. Not yet. 

Douglas,

What is the 2.5GHz input clock? Are you using this as the reference clock for the DAC PLL? What Altera device? We currently are having trouble with the Arria V running at 12.5Gsps as well. It may be a power issue with the FPGA. Have you contacted Altera regarding this problem? Does the problem go away with a slower serdes rate?

Regards,

Jim

Yes the 2.5 GHz clock is the reference clock (DACCLK A10, A9)

FPGA family is the Arria 10

Material is Megtron 6

We haven't attempted a slower serdes rate.

We have contacted Altera but am looking for documentation on using EQOVER and EQUNDER?