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DAC38J84EVM: DAC has no output, even Tx works and GUI shows no alarms

Yawen Luo
Prodigy 100 points
Part Number: DAC38J84EVM
Other Parts Discussed in Thread: LMK04828, DAC38J84

I'm using Xilinx ZCU102 board to transmit data through JESD204 to DAC38J84EVM.

My settings:

Using DAC38J84EVM onboard LMK chip to generate Core Clock and SysRef for both DAC and FPGA.

LMFK: 4,4,2,10;             FPGA clock: 184.32MHz;          SerDes Line Rate: 7.3728MHz;            interpolation: 4;

I just use the default setting in the Quick Start page, and click the button 1 Program directly without configuring any other parameters in the DAC GUI. My FPGA JESD Tx core is configured accordingly.(I think I set those registers correctly)

My status is DAC has no output. FPGA after received asserted SYNC from DAC, start to send ILA sequence and followed by data transmission. As following figure shows, the Tx seems works fine so far.

As for DAC part, my Alarms and Errors Page shows everything goes well(I'm only using LANE 0 -3) .

But I still could not get any output. I've shorted the TXENABLE jumper. Does anyone know where I can debug from? Are there any potential registers in the DAC GUI I should set separately?  Please help, any info or intuition will be appreciated.

  • 0
    TI__Genius 12780 points

    Hi Yawen,

    One of our device experts is looking into your issue, and will be back with you soon.

    Best Regards,

    Dan

  • 0
    TI__Guru* 91947 points

    Yawen,

    Make sure jumper JP4 has a shunt between 2-3, jumper JP1 has a shunt between pins 1-2. LED D7 should be on indicating the LMK PLL2 is locked. Are you able to read back the DAC registers properly?  How much current can your 5V supply provide to the DAC EVM? Do you get an output if you just use the DAC NCO (see attached document for this test)? This will verify power, clocks, and SPI are working properly.

    Also check the status of SYNC. I think the SYNC routing is missing on the FMC of the Zync board if I remember correctly.

    Regards,

    Jim

    0624.DAC38J84 100MHz NCO Test.pptx 

  • 0 in reply to jim s
    Prodigy 100 points

    Thanks for your time!

    I did the following checks as you suggested, all of them are set.

    I checked the JP4 and JP1, LED D7, they function well.

    I can read back the DAC registers.

    My 5V supply provides 0.67A current.

    I also can get output from DAC NCO followed by the pptx file you sent.

    And you're right, ZCU102 board is missing the SYNC routing, and I'm currently using TI TSW14J10 (interposer board) to re-route the SYNC signal. So the sync problem should be fine, and I monitored the SYNC signal on FPGA via both LED and Xilinx ILA(Internal Logic Analyzer), it asserted well once I trigger the LMK04828 SYSREF.

    I'm attaching more details about my design for your reference.

    In my FPGA design:

    my 184.32MHz refclk sourced from LMK DCLK0.

    my tx_core_clk is also set as 184.32MHz, and derived from refclk.

    My jesd ip core is configured based on the parameters shown as following(which is auto-generated after I click the button 1 on Quick Start page). I only refer to the red block region. 

    specific configurations as follows:

    Including the JESD ip GUI settings, I also using AXI4-Lite bus write register ILA Config Data 4 register(which set N, N', and M).

    Actually, I don't fully understand other parameters in the DAC GUI (excluding the DAC3XJ8X control JESD block page), I think maybe there are some important parameter need to be adjusted accordingly. Again, In the DAC GUI, I only input:

    EVM clocking Mode: Onboard

    Device: DAC38j84

    DAC data input rate: 368.64 MSPS

    Number of SerDes Lines: 4

    Interpolation: 4

    Then everything else is auto-generated by GUI. And I configure my FPGA JESD204 IP Core (captured above) according to the DAC3XJ8X control JESD block page red area(captured above), and status block in Quick Start Page below.

    That's basically my situation. My FPGA Tx Core seems working, it keeps sending data after CGS and ILAS. But never observe any output. It's always 690mV constant current. Do you have any idea?

    Or if possible, whichever is convenient, can you send me some tested/passed example configurations, any combo of DAC input rate, lanes, interpolation is ok for me, I just wanna see the communication working.

    Thanks for your time! Best,

    Yawen

  • 0 in reply to Yawen Luo
    TI__Guru* 91947 points

    8053.KCU105 HSDC Pro User's Guide.pdfKCU105 + ADC and DAC38J8x Configuration.pptxYawen,

    Attached are some examples using the DAC EVM with a KCU105. We do not have any examples using the ZCU board. 

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points

    Thanks for your help, Jim!

    Best,

    Yawen